CY7C1357A View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
CY7C1357A
Cypress Semiconductor
CY7C1357A Datasheet PDF : 28 Pages
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CY7C1357A
CY7C1355A
Pin Descriptions (CY7C1357A) (continued)
512K × 18
TQFP Pins
88
Name
WEN
89
CLK
98,
CE1, CE3
92
97
CE2
86
OE
85
ADV/
LD
31
MODE
64
ZZ
58, 59, 62, 63, 68,
69, 72, 73, 74
8, 9, 12, 13, 18, 19,
22, 23, 24
15, 16, 41, 65, 91
5, 10, 14, 17, 21, 26,
40, 55, 60, 66, 67,
71, 76, 90
4, 11, 20, 27, 54, 61,
70, 77
1-3, 6, 7, 25, 28-30,
51-53, 56, 57, 75,
78, 79, 84, 95, 96,
38,39,42,43
DQa
DQb
VCC
VSS
VCCQ
NC
Type
Input-
Synchronous
Input-
Clock
Input-
Synchronous
Input-
Synchronous
Input-
Asynchronous
Input-
Synchronous
Input
Input
Asynchronous
Input/
Output-
Synchronous
Description
Read Write: WEN signal is a synchronous input that identifies whether
the current loaded cycle and the subsequent burst cycles initiated by
ADV/LD is a Read or Write operation. The data bus activity for the current
cycle takes place one clock cycle later.
Clock: This is the clock input to CY7C1357A. Except for OE, ZZ and
MODE, all timing references for the device are made with respect to the
rising edge of CLK.
Synchronous Active Low Chip Enable: CE1 and CE3 are used with CE2
to enable the CY7C1357A. CE1 or CE3 sampled HIGH or CE2 sampled
LOW, along with ADV/LD LOW at the rising edge of clock, initiates a
deselect cycle. The data bus will be High-Z one clock cycle after chip
deselect is initiated.
Synchronous Active High Chip Enable: CE2 is used with CE1 and CE3
to enable the chip. CE2 has inverted polarity but otherwise is identical to
CE1 and CE3.
Asynchronous Output Enable: OE must be LOW to read data. When
OE is HIGH, the I/O pins are in high-impedance state. OE does not need
to be actively controlled for read and write cycles. In normal operation, OE
can be tied LOW.
Advance/Load: ADV/LD is a synchronous input that is used to load the
internal registers with new address and control signals when it is sampled
LOW at the rising edge of clock with the chip is selected. When ADV/LD
is sampled HIGH, then the internal burst counter is advanced for any burst
that was in progress. The external addresses and WEN are ignored when
ADV/LD is sampled HIGH.
Burst Mode: When MODE is HIGH or NC, the interleaved burst sequence
is selected. When MODE is LOW, the linear burst sequence is selected.
MODE is a static DC input.
Sleep Enable: This active HIGH input puts the device in low power
consumption standby mode. For normal operation, this input has to be
either LOW or NC.
Data Inputs/Outputs: Both the data input path and data output path are
registered and triggered by the rising edge of CLK. Byte “a” is DQa pins;
Byte “b” is DQb pins.
Supply
Ground
Power Supply: +3.3V –5% and +5%.
Ground: GND.
I/O Power Supply Power supply for the I/O circuitry.
–
No Connect: These signals are not internally connected. It can be left
floating or be connected to VCC or to GND.
Document #: 38-05265 Rev. *A
Page 7 of 28
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