CY7C1357A View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
CY7C1357A
Cypress Semiconductor
CY7C1357A Datasheet PDF : 28 Pages
| |||
CY7C1357A
CY7C1355A
ZZ Mode Electrical Characteristics
IDDZZ
tZZS
tZZREC
Parameter
Description
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
Test Conditions
ZZ > VDD – 0.2V
ZZ > VDD – 0.2V
ZZ < 0.2V
Min.
2tCYC
Max.
10
2tCYC
Unit
mA
ns
ns
Truth Table[6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17]
Operation
Previous Address
Cycle
Used WEN ADV/LD CE
Deselect Cycle
Continue Deselect/NOP[18]
X
X
Deselect
X
X
L
H
X
H
X
Read Cycle (Begin Burst)
X
External H
L
L
Read Cycle (Continue Burst)[18]
Read
Next
X
H
X
Dummy Read (Begin Burst)[19]
X
External H
L
L
Dummy Read (Continue Burst)[18, 19] Read
Next
X
H
X
Write Cycle (Begin Burst)
X
External L
L
L
Write Cycle (Continue Burst)[18]
Write
Next
X
H
X
Abort Write (Begin Burst)[19]
X
External L
L
L
Abort Write (Continue Burst)[18, 19]
Write
Next
X
H
X
Ignore Clock Edge/NOP[20]
X
X
X
H
X
CEN
L
L
L
L
L
L
L
L
L
L
H
BWx
X
X
X
X
X
X
L
L
H
H
X
DQ
OE (1 cycle later)
X
High-Z
X
High-Z
X
Q
X
Q
H
High-Z
H
High-Z
X
D
X
D
X
High-Z
X
High-Z
X
-
IEEE 1149.1 Serial Boundary Scan (JTAG)
Disabling the JTAG Feature
Overview
It is possible to use this device without using the JTAG feature.
To disable the TAP controller without interfering with normal
This device (except for CY7C1357A) incorporates a serial operation of the device, TCK should be tied LOW (VSS) to
boundary scan access port (TAP). This port is designed to prevent clocking the device. TDI and TMS are internally pulled
operate in a manner consistent with IEEE Standard up and may be unconnected. They may alternately be pulled
1149.1-1990 (commonly referred to as JTAG), but does not up to VCC through a resistor. TDO should be left unconnected.
implement all of the functions required for IEEE 1149.1 Upon power-up the device will come up in a reset state which
compliance. Certain functions have been modified or elimi- will not interfere with the operation of the device.
nated because their implementation places extra delays in the
critical speed path of the device. Nevertheless, the device Test Access Port
supports the standard TAP controller architecture (the TAP
controller is the state machine that controls the TAPs TCK—Test Clock (INPUT)
operation) and can be expected to function in a manner that
does not conflict with the operation of devices with IEEE
Standard 1149.1-compliant TAPs. The TAP operates using
LVTTL/ LVCMOS logic level signaling.
Clocks all TAP events. All inputs are captured on the rising
edge of TCK and all outputs propagate from the falling edge
of TCK.
Notes:
6. This assumes that CEN, CE, CE2, and CE2 are all True.
7. All addresses, control and data-in are only required to meet set-up and hold time with respect to the rising edge of clock. Data out is valid after a clock-to-data
delay from the rising edge of clock.
8. DQc and DQd apply to 256Kx36 device only.
9. L means logic LOW. H means logic HIGH. X means “Don’t Care.” High-Z means High Impedance. BWx = L means [BWa*BWb*BWc*BWd] equals LOW. BWx
= H means [BWa*BWb*BWc*BWd] equals HIGH. BWc and BWd apply to 256K × 36 device only.
10. CE = H means CE and CE2 are LOW along with CE2 being HIGH. CE = L means CE or CE2 is HIGH or CE2 is LOW. CE = X means CE, CE2, and CE2 are
“Don’t Care.”
11. BWa enables WRITE to byte “a” (DQa pins). BWb enables WRITE to byte “b” (DQb pins). BWc enables WRITE to byte “c” (DQc pins). BWd enables WRITE to
byte “d” (DQd pins). DQc, DQd, BWc, and BWd apply to 256K × 36 device only.
12. The device is not in Sleep Mode, i.e., the ZZ pin is LOW.
13. During Sleep Mode, the ZZ pin is HIGH and all the address pins and control pins are “Don’t Care.” The Sleep Mode can only be entered one cycle after the
WRITE cycle, otherwise the WRITE cycle may not be completed.
14. All inputs, except OE, ZZ, and MODE pins, must meet set-up time and hold time specification against the clock (CLK) LOW-to-HIGH transition edge.
15. OE may be tied to LOW for all the operation. This device automatically turns off the output driver during WRITE cycle.
16. Device outputs are ensured to be in High-Z during device power-up.
17. This device contains a two-bit burst counter. The address counter is incremented for all Continue Burst cycles. Address wraps to the initial address every fourth
burst cycle.
18. Continue Burst cycles, whether READ or WRITE, use the same control signals. The type of cycle performed, READ or WRITE, depends upon the WEN control
signal at the BEGIN BURST cycle. A Continue Deselect cycle can only be entered if a Deselect cycle is executed first.
19. Dummy Read and Abort WRITE cycles can be entered to set up subsequent READ or WRITE cycles or to increment the burst counter.
20. When an Ignore Clock Edge cycle enters, the output data (Q) will remain the same if the previous cycle is READ cycle or remain High-Z if the previous cycle is
WRITE or Deselect cycle.
Document #: 38-05265 Rev. *A
Page 9 of 28
Share Link: