CY7C1360B View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
CY7C1360B Datasheet PDF : 34 Pages
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CY7C1360B
CY7C1362B
CY7C1362B–Pin Definitions (continued)
TQFP
TQFP
3-Chip 2-Chip
Name Enable Enable BGA
fBGA
I/O
Description
ADSP
84
84
A4
B9
Input- Address Strobe from Processor, sampled on
Synchronous the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the device
are captured in the address registers. A1, A0 are
also loaded into the burst counter. When ADSP
and ADSC are both asserted, only ADSP is recog-
nized. ASDP is ignored when CE1 is deasserted
HIGH.
ADSC
85
85
P4
A8
Input- Address Strobe from Controller, sampled on
Synchronous the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the device
are captured in the address registers. A1, A0 are
also loaded into the burst counter. When ADSP
and ADSC are both asserted, only ADSP is recog-
nized.
ZZ
64
64
T7
H11
Input- ZZ “Sleep” Input, active HIGH. When asserted
Asynchronous HIGH places the device in a non-time-critical
“sleep” condition with data integrity preserved. For
normal operation, this pin has to be LOW or left
floating. ZZ pin has an internal pull-down.
DQs,
DQPs
VDD
58,59,62,
63,68,69,
72,73,8,9,
12,13,18,
19,22,23,
74,24
15,41,65,
91
58,59,62,
63,68,69,
72,73,8,9,
12,13,18,
19,22,23,
74,24
15,41,65,
91
P7,K7, J10,K10,
I/O-
Bidirectional Data I/O lines. As inputs, they feed
G7,E7, L10,M10, Synchronous into an on-chip data register that is triggered by the
F6,H6,L6, D11,E11,
rising edge of CLK. As outputs, they deliver the
N6,D1, F11,G11,J1,
data contained in the memory location specified by
H1,L1, K1,L1,M1,D
the addresses presented during the previous clock
N1,E2, 2,E2,F2,
rise of the a Read cycle. The direction of the pins
G2,K2, G2,C11,N1
is controlled by OE. When OE is asserted LOW,
M2,D6,
the pins behave as outputs. When HIGH, DQs and
P2
DQPX are placed in a three-state condition.
C4,J2,J4, D4,D8,E4,E Power Supply Power supply inputs to the core of the device.
J6,R4 8,F4,F8,
G4,G8,H4,
H8,J4,J8,
K4,K8,L4,
L8,M4,M8
VSS
17,40,67, 17,40,67, D3,D5, H2,C4,C5, Ground Ground for the core of the device.
90
90 E5,E3,F3, C6,C7,C8,
F5,G5, D5,D6,D7,E
H3,H5, 5,E6,E7,
K3,K5,L3, F5,F6,F7,
M3,M5, G5,G6,G7,
N3,N5, H5,H6,H7,J
P3,P5 5,J6,J7,
K5,K6,K7,
L5,L6,L7,
M5,M6,M7,
N4,N8
VSSQ
5,10,21,26, 5,10,21,26,
-
55,60,71, 55,60,71,
76
76
-
I/O Ground Ground for the I/O circuitry.
Document #: 38-05291 Rev. *C
Page 10 of 34
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