CY7C1360B View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
CY7C1360B Datasheet PDF : 34 Pages
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CY7C1360B
CY7C1362B
CY7C1360B–Pin Definitions
TQFP
TQFP
3-Chip 2-Chip
Name Enable Enable BGA
fBGA
I/O
Description
A0, A1, A
37,36,32,
33,34,35,
43,44,45,
46,47,48,
49,50,81,
82,99,100
37,36,32, P4,N4, R6,P6,A2,
Input- Address Inputs used to select one of the 256K
33,34,35, A2,C2, A10,B2, Synchronous address locations. Sampled at the rising edge of
44,45,46, R2,3A, B10,P3,P4,
47,48,49, B3,C3, P8,P9,P10,
50,81,82, T3,T4,A5, P11,R3,R4,
the CLK if ADSP or
CE2, and CE3[2]are
ADSC is active LOW, and CE1,
sampled active. A1, A0 are fed
to the two-bit counter..
92,99,100 B5,C5, R8,R9,R10,
T5,A6,B6, R11
C6,R6
BWA,BWB
93,94,95,
96
93,94,95,
96
BWC,BWD
GW
88
88
BWE
87
87
L5,G5,
G3,L3
H4
M4
B5,A5,A4,
Input- Byte Write Select Inputs, active LOW. Qualified
B4
Synchronous with BWE to conduct Byte Writes to the SRAM.
Sampled on the rising edge of CLK.
B7
Input- Global Write Enable Input, active LOW. When
Synchronous asserted LOW on the rising edge of CLK, a global
Write is conducted (ALL bytes are written,
regardless of the values on BWX and BWE).
A7
Input- Byte Write Enable Input, active LOW. Sampled
Synchronous on the rising edge of CLK. This signal must be as-
serted LOW to conduct a Byte Write.
CLK
89
89
K4
B6
Input- Clock Input. Used to capture all synchronous
Clock inputs to the device. Also used to increment the
burst counter when ADV is asserted LOW, during a
burst operation.
CE1
98
98
E4
A3
Input- Chip Enable 1 Input, active LOW. Sampled on the
Synchronous arisnidngCeEd3g[2e] toofsCeLleKc.t/Udesesedleinctcothnejudnecvtiiocne.wAitDhSCPEi2s
ignored if CE1 is HIGH.
CE2
97
97
B2
B3
Input- Chip Enable 2 Input, active HIGH. Sampled on
Synchronous the rising edge of CLK. Used in conjunction with
CE1 and CE3[2] to select/deselect the device.
CE3[2]
92
-
-
A6
Input- Chip Enable 3 Input, active LOW. Sampled on the
Synchronous rising edge of CLK. Used in conjunction with CE1
and CE2 to select/deselect the device. Not available
for AJ package version. Not connected for BGA.
Where referenced, CE3[2] is assumed active
throughout this document for BGA.
OE
86
86
F4
B8
Input- Output Enable, asynchronous input, active
Asynchro- LOW. Controls the direction of the I/O pins. When
nous LOW, the I/O pins behave as outputs. When
deasserted HIGH, I/O pins are three-stated, and act
as input data pins. OE is masked during the first
clock of a read cycle when emerging from a
deselected state.
ADV
83
83
G4
A9
Input- Advance Input signal, sampled on the rising
Synchronous edge of CLK, active LOW. When asserted, it
automatically increments the address in a burst
cycle.
Document #: 38-05291 Rev. *C
Page 6 of 34
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