LS7061 View Datasheet(PDF) - LSI Corporation
Part Name
Description
Manufacturer
LS7061 Datasheet PDF : 7 Pages
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DYNAMIC ELECTRICAL CHARACTERISTICS: (Refer to Figure 3, Timing Diagram)
(VDD = +5V ± 5%, VSS = 0V, TA = 0˚C to +70˚C unless otherwise noted.)
PARAMETER
Count Frequency
(All Count inputs)
Count Pulse Width
(All Count Inputs)
SYMBOL
MIN
fc
DC
tCPW
30
MAX
15
-
UNIT
MHz
ns
Count Rise & Fall time
tr, tf
-
30
µs
(Pins 2, 16)
Count Ripple Time
(Pins 2 - LS7061)
tCR
-
4
µs
Count Ripple Time
(Pin 13 - LS7061)
(Pins 2,13 - LS7063)
RESET Pulse Width
(All Counter Stages
Fully Reset)
tCR
-
2
µs
tRPW
500
-
ns
RESET Removal Time
tRR
-
250
ns
(Reset Removed From
All Counter Stages)
SCAN Frequency
SCAN Pulse Wildth
fSC
-
1
MHz
tSCPW
500
-
ns
SCAN RESET/LOAD
tRSCPW
1
-
µs
Pulse Width
(All latches loaded and
Scan Counter Reset to
Least Significant Byte)
SCAN RESET/LOAD
tRSCR
-
250
ns
Removal Time
(Reset Removed from
Scan Counter; Load
Command Removed
From Latches)
Output Disable
Delay Time
(B0 - B7)
tDOD
-
200
ns
Output ENABLE
Delay Time
(B0 - B7)
tDOE
-
200
ns
Output Delay Time
CASCADE ENABLE
tDCE
-
300
ns
CONDITIONS
-
Measured at 50% point,
Max tr, tf = 10ns
-
Transition from32 ones to 32 zeros
from negative edge of count pulse
Transition of 16 bits from
all ones to all zeros from negative edge
of count pulse
Measured at 50% point
Max tr, tf = 200ns
Measured from RESET signal at VIH
Measured at 50% point
Max tr, tf = 100ns
Measured at 50% point
Max tr, tf = 200ns
Measured from SCAN RESET/
LOAD at VIH
Transition to Output High
Impedance State Measured
From Scan at VIL or
ENABLE at VIH
Transition to Valid On State
Measured from Scan at VIH
and ENABLE at VIL; Delay to
Valid Data Levels for COL =10pF
and one TTL Load or Valid Data
Currents for High Capacitance Loads
Negative Transition from Scan at VIL
and ST5 of Scan Counter or Positive
Transition From SCAN RESET/LOAD at
VIL to Valid Data Levels for COL = 10pF
and one TTL Load
7061/63-083198-4
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