AC Test Conditions
Parameter Description
C1
Capacitor 1
C2
Capacitor 2
R1
Resistor 1
R2
Resistor 2
R3
Resistor 3
R4
Resistor 4
RTH
Resistor Thevenin
VTH
Voltage Thevenin
Thermal Resistance5
Parameter
ΘJA
ΘJC
Description
Thermal Resistance
(Junction to
Ambient)
Thermal Resistance
(Junction to Case)
Conditions
Still Air, soldered on a
3 × 4.5 square inch,
two–layer printed
circuit board
AC Electrical Characteristics6 7 8
Parameter
Description
tRC
tAA
tOHA
Read Cycle Time
Address to Data Valid
Data Hold from Address
Change
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
tPD
tWC
tSCE
tAW
CE to Data Valid
OE to Data Valid
OE to Low Z
OE to High Z
CE to Low Z
CE to High Z
CE to Power–Up
CE to Power–Down
Write Cycle Time
CE to Write End
Address Set–Up to Write
End
tHA
Address Hold from Write
End
12 ns
Min Max
12
–
–
12
3
–
–
12
–
5
0
–
–
5
3
–
–
5
0
–
–
12
12
–
9
–
9
–
0
–
Nom.
30
5
480
255
480
255
167
1.73
TSOP I
88.6
21.94
15 ns
Min Max
15
–
–
15
3
–
–
15
–
7
0
–
–
7
3
–
–
7
0
–
–
15
15
–
10
–
10
–
0
–
SOJ
79
41.42
20 ns
Min Max
20
–
–
20
3
–
–
20
–
9
0
–
–
9
3
–
–
9
0
–
–
20
20
–
15
–
15
–
0
–
CY7C199C
Unit
pF
Ω
DIP
TBD
TBD
V
Unit
°C/W
25 ns
Min Max Unit
25
–
ns
–
25 ns
3
–
ns
–
25 ns
–
9
ns
0
–
ns
–
9
ns
3
–
ns
–
9
ns
0
–
ns
–
20 ns
25
–
ns
15
–
ns
15
–
ns
0
–
ns
Notes:
5. Test Conditions assume a transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
7. The internal write time of the memory is defined by the overlap of
CE LOW and WE LOW. CE and WE must be LOW to initiate a
write, and the transition of any of these signals can terminate the
write. The input data set–up and hold timing should be referenced
to the leading edge of the signal that terminates the write.
8. tHZOE, tHZCE, tHZWE are specified as in part (b) of the A/C Test
Loads. Transitions are measured ± 200 mV from steady state volt-
age.
Document #: 38-05408 Rev. *A
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