MCM63P531 View Datasheet(PDF) - Motorola => Freescale
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Description
Manufacturer
MCM63P531 Datasheet PDF : 16 Pages
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AC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V + 10%, – 5%, TJ = 20 to 110°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ns
Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . . . See Figure 1 Unless Otherwise Noted
READ/WRITE CYCLE TIMING (See Notes 1, 2, 3, and 4)
MCM63P531–4.5 MCM63P531–7 MCM63P531–8 MCM63P531–9
100 MHz
75 MHz
66 MHz
60 MHz
Parameter
Symbol
Min
Max
Min Max Min Max Min Max Unit
Cycle Time
Clock High Pulse Width
Clock Low Pulse Width
Clock Access Time
Output Enable to Output
Valid
tKHKH
10
—
13.3
—
15
—
16.6
—
ns
tKHKL
3.2
—
4.5
—
5
—
5
—
ns
tKLKH
3.2
—
4.5
—
5
—
5
—
ns
tKHQV
—
4.5
—
7
—
8
—
9
ns
tGLQV
—
4.5
—
6
—
6
—
7
ns
Clock High to Output Active tKHQX1
0
—
Clock High to Output
Change
tKHQX2
1.5
—
0
—
2
—
0
—
2
—
0
—
ns
2
—
ns
Output Enable to Output
Active
tGLQX
0
—
0
—
0
—
0
—
ns
Output Disable to Q High–Z tGHQZ
—
5.5
—
7
—
8
—
9
ns
Clock High to Q High–Z
tKHQZ
1.5
10
2
7
2
8
2
9
ns
Setup Times:
Address tADKH
2.0
—
2.5
—
2.5
—
2.5
—
ns
ADSP, ADSC, ADV tADSKH
Data In tDVKH
Write tWVKH
Chip Enable tEVKH
Hold Times:
Address tKHAX
0.5
—
0.5
—
0.5
—
0.5
—
ns
ADSP, ADSC, ADV tKHADSX
Data In tKHDX
Write tKHWX
Chip Enable tKHEX
NOTES:
1. Write applies to all SBx, SW, and SGW signals when the chip is selected and ADSP high.
2. Chip Enable applies to all SE1, SE2 and SE3 signals whenever ADSP or ADSC is asserted.
3. All read and write cycle timings are referenced from K or G.
4. G is a don’t care after write cycle begins. To prevent bus contention, G should be negated prior to start of write cycle.
5. Tested per AC Test Load.
6. Measured at ± 200 mV from steady state. Tested per High–Z Test Load.
7. This parameter is sampled and is not 100% tested.
Notes
5
5
5, 7
5, 7
5, 7
6, 7
6, 7
4
4
OUTPUT
Z0 = 50 Ω
RL = 50 Ω
OUTPUT
351 Ω
+ 3.3 V
317 Ω
5 pF
(a) AC Test Load
VT = 1.5 V
(b) High–Z Test Load
Figure 1. Test Loads
MCM63P531
8
MOTOROLA FAST SRAM
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