CY7C1335 View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
CY7C1335 Datasheet PDF : 15 Pages
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1CY 7C13 35
fax id: 1045
PRELIMINARY
CY7C1335
32K x 32 Synchronous-Pipelined Cache RAM
Features
Functional Description
• Low (660 µW) standby power (f=0, L version)
• Supports 100-MHz bus for Pentium™ and PowerPC™
operations with zero wait states
• Fully registered inputs and outputs for pipelined oper-
ation
• 32K x 32 common I/O architecture
• Single 3.3V power supply
• Fast Clock-to-output times
— 5.5ns (for 100-MHz device)
— 7.0 ns (for 75-MHz device)
— 8.5 ns (for 66-MHz device)
— 10 ns (for 60-MHz device)
• User-selectable burst counter supporting Intel Pentium
interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• JEDEC-standard 100 TQFP pinout
• “ZZ” Sleep Mode option and Stop Clock option
Logic Block Diagram
CLK
ADV
ADSC
ADSP
A[14:0]
15
GW
BWE
BW3
BW2
BW1
BW0
CE1
CE2
CE3
MODE
(A0,A1) 2
BURST Q0
CE COUNTER
CLR
Q1
Q
CE
D
ADDRESS
REGISTER
13
D DQ[31:24] Q
BYTEWRITE
REGISTERS
D DQ[23:16] Q
BYTEWRITE
REGISTERS
D DQ[15:8] Q
BYTEWRITE
REGISTERS
D DQ[7:0] Q
BYTEWRITE
REGISTERS
D
CE
ENABLE
REGISTER
Q
CLK
The CY7C1335 is 3.3V 32K by 32 synchronous-pipelined
cache SRAM designed to support zero wait state secondary
cache with minimal glue logic.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
Maximum access delay from the clock rise is 5.5ns (100 MHz
device). A 2-bit on-chip wraparound burst counter captures
the first address in a burst sequence and automatically incre-
ments the address for the rest of the burst access.
The CY7C1335 supports either the interleaved burst se-
quence used by the Intel Pentium processor or a linear burst
sequence used by processors such as the PowerPC. The
burst sequence is selected through the MODE pin. Accesses
can be initiated by asserting either the processor address
strobe (ADSP) or the controller address strobe (ADSC) at
clock rise. Address advancement through the burst sequence
is controlled by the ADV input.
Byte write operations are qualified with the four Byte Write
Select (BW[0-3]) inputs. A Global Write Enable (GW) overrides
all byte write inputs and writes data to all four bytes. All writes
are conducted with on-chip synchronous self-timed write cir-
cuitry.
Three synchronous chip selects (CE1, CE2, CE3) and an asyn-
chronous output enable (OE) provide for easy bank selection
and output three-state control. In order to provide proper data
during depth expansion, OE is masked during the first clock of
a read cycle when emerging from a deselected state.
13
15
32KX32
MEMORY
ARRAY
32
32
D
Q
ENABLE DELAY
REGISTER
CLK
OUTPUT
REGISTERS
CLK
INPUT
REGISTERS
CLK
OE
ZZ
SLEEP
CONTROL
DQ[31:0]
Pentium is a trademark of Intel Corporation.
PowerPC is a trademark of IBM Corporation.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
April 1995 – Revised January 13, 1997
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