LHF32KZ5 View Datasheet(PDF) - Sharp Electronics

Part Name

Description

Manufacturer

LHF32KZ5

Flash Memory 32M (× 8 or ×16)

Sharp Electronics 

sharp

LHF32KZ5

5

Table 2. Pin Descriptions

Symbol Type

Name and Function

ADDRESS INPUTS: Inputs for addresses during read and write operations. Addresses are

internally latched during a write cycle.

A0-A20

INPUT

A0: Byte Select Address. Not used in x16 mode(can be floated).

A1-A4: Column Address. Selects 1 of 16 bit lines.

A5-A15: Row Address. Selects 1 of 2048 word lines.

A16-A20 : Block Address.

DATA INPUT/OUTPUTS:

DQ0-DQ7:Inputs data and commands during CUI write cycles; outputs data during memory

array, status register, query, and identifier code read cycles. Data pins float to high-

DQ0-DQ15

INPUT/

OUTPUT

impedance when the chip is deselected or outputs are disabled. Data is internally latched

during a write cycle.

DQ8-DQ15:Inputs data during CUI write cycles in x16 mode; outputs data during memory

array read cycles in x16 mode; not used for status register, query and identifier code read

mode. Data pins float to high-impedance when the chip is deselected, outputs are

BE0#,

BE1L#

BE1H#

INPUT

disabled, or in x8 mode(Byte#=VIL). Data is internally latched during a write cycle.

BANK ENABLE: Activates the device’s control logic, input buffers, decoders, and sense

amplifiers. When BE0# and BE1L# "low", bank0 is in active. When BE0# and BE1H# are

"low", bank1 is in active. BE0# and BE1L#, BE1H# must not be low at the same time.

RESET/DEEP POWER-DOWN: Puts the device in deep power-down mode and resets

RP#

INPUT

internal automation. RP# VIH enables normal operation. When driven VIL, RP# inhibits

write operations which provides data protection during power transitions. Exit from deep

power-down sets the device to read array mode.

OE# INPUT OUTPUT ENABLE: Gates the device’s outputs during a read cycle.

WE#

INPUT

WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are

latched on the rising edge of the WE# pulse.

STS (RY/BY#): Indicates the status of the internal WSM. When configured in level mode

(default mode), it acts as a RY/BY# pin. When low, the WSM is performing an internal

OPEN operation (block erase, bank erase, (multi) word/byte write or block lock-bit configuration).

STS DRAIN STS High Z indicates that the WSM is ready for new commands, block erase is

OUTPUT suspended, and (multi) word/byte write is inactive, (multi) word/byte write is suspended or

the device is in deep power-down mode. For alternate configurations of the STATUS pin,

see the Configuration command.

WP#

INPUT

WRITE PROTECT: Master control for block locking. When VIL, Locked blocks can not be

erased and programmed, and block lock-bits can not be set and reset.

BYTE#

BYTE ENABLE: BYTE# VIL places device in x8 mode. All data is then input or output on

INPUT DQ0-7, and DQ8-15 float. BYTE# VIH places the device in x16 mode , and turns off the A0

input buffer.

BLOCK ERASE, BANK ERASE, (MULTI) WORD/BYTE WRITE, BLOCK LOCK-BIT

CONFIGURATION POWER SUPPLY: For erasing array blocks, writing bytes or

VPP SUPPLY configuring block lock-bits. With VPP≤VPPLK, memory contents cannot be altered. Block

erase, bank erase, (multi) word/byte write and block lock-bit configuration with an invalid

VPP (see DC Characteristics) produce spurious results and should not be attempted.

DEVICE POWER SUPPLY: Internal detection configures the device for 2.7V, 3.3V or 5V

operation. To switch from one voltage to another, ramp VCC down to GND and then ramp

VCC SUPPLY VCC to the new voltage. Do not float any power pins. With VCC≤VLKO, all write attempts to

the flash memory are inhibited. Device operations at invalid VCC voltage (see DC

Characteristics) produce spurious results and should not be attempted.

GND SUPPLY GROUND: Do not float any ground pins.

NC

NO CONNECT: Lead is not internal connected; it may be driven or floated.

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