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CYM1851PZ-25C View Datasheet(PDF) - Cypress Semiconductor

Part Name
Description
Manufacturer
CYM1851PZ-25C
Cypress
Cypress Semiconductor Cypress
CYM1851PZ-25C Datasheet PDF : 9 Pages
1 2 3 4 5 6 7 8 9
CYM1851
AC Test Loads and Waveforms
R1 481
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
(a)
R1 481
5V
R2 OUTPUT
255
5 pF
INCLUDING
JIG AND
SCOPE
(b)
R2
255
3.0V
GND
< 5 ns
Equivalent to: THÉVENIN EQUIVALENT
OUTPUT
167
1.73V
ALL INPUT PULSES
90%
10%
90%
10%
< 5 ns
Switching Characteristics Over the Operating Range[3]
1851-12
1851-15
Parameter
Description
Min. Max. Min. Max. Unit
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACS
CS LOW to Data Valid
tDOE
OE LOW to Data Valid
tLZOE
OE LOW to Low Z
tHZOE
tLZCS
tHZCS
OE HIGH to High Z
CS LOW to Low Z[4]
CS HIGH to High Z[4, 5]
tPD
CS HIGH to Power-Down
WRITE CYCLE[6]
12
15
ns
12
15
ns
3
3
ns
12
15
ns
7
8
ns
0
0
ns
7
8
ns
3
3
ns
7
8
ns
12
15
ns
tWC
Write Cycle Time
12
15
ns
tSCS
CS LOW to Write End
9
10
ns
tAW
Address Set-Up to Write End
9
10
ns
tHA
Address Hold from Write End
0
0
ns
tSA
Address Set-Up to Write Start
1
1
ns
tPWE
WE Pulse Width
10
12
ns
tSD
Data Set-Up to Write End
7
8
ns
tHD
Data Hold from Write End
1
1
ns
tLZWE
tHZWE
WE HIGH to Low Z
WE LOW to High Z[5]
3
3
ns
0
7
0
8
ns
Notes:
3. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
4. At any given temperature and voltage condition, tHZCS is less than tLZCS for any given device. These parameters are guaranteed and not 100% tested.
5. tHZCS and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured ±500 mV from steady-state voltage.
6. The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
Document #: 38-05274 Rev. **
Page 3 of 9

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