CYRF69103(2007) View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
CYRF69103 Datasheet PDF : 73 Pages
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CYRF69103
The CYRF69103 IC supports packet length of up to 40 bytes;
interrupts are provided to allow an MCU to use the transmit
and receive buffers as FIFOs. When transmitting a packet
longer than 16 bytes, the MCU can load 16 bytes initially, and
add further bytes to the transmit buffer as transmission of data
creates space in the buffer. Similarly, when receiving packets
longer than 16 bytes, the MCU must fetch received data from
the FIFO periodically during packet reception to prevent it from
overflowing.
Auto Transaction Sequencer (ATS)
The CYRF69103 IC provides automated support for trans-
mission and reception of acknowledged data packets.
When transmitting a data packet, the device automatically
starts the crystal and synthesizer, enters transmit mode,
transmits the packet in the transmit buffer, and then automati-
cally switches to receive mode and waits for a handshake
packet—and then automatically reverts to sleep mode or idle
mode when either an ACK packet is received, or a time-out
period expires.
Similarly, when receiving in transaction mode, the device waits
in receive mode for a valid packet to be received, then
automatically transitions to transmit mode, transmits an ACK
packet, and then switches back to receive mode to await the
next packet. The contents of the packet buffers are not
affected by the transmission or reception of ACK packets.
In each case, the entire packet transaction takes place without
any need for MCU firmware action; to transmit data the MCU
simply needs to load the data packet to be transmitted, set the
length, and set the TX GO bit. Similarly, when receiving
packets in transaction mode, firmware simply needs to retrieve
the fully received packet in response to an interrupt request
indicating reception of a packet.
Interrupts
The radio function provides an interrupt (IRQ) output, which is
configurable to indicate the occurrence of various different
events. The IRQ pin may be programmed to be either active
high or active low, and be either a CMOS or open drain output.
The radio function features three sets of interrupts: transmit,
receive, and system interrupts. These interrupts all share a
single pin (IRQ), but can be independently enabled/disabled.
In transmit mode, all receive interrupts are automatically
disabled, and in receive mode all transmit interrupts are
automatically disabled. However, the contents of the enable
registers are preserved when switching between transmit and
receive modes.
If more than one radio interrupt is enabled at any time, it is
necessary to read the relevant status register to determine
which event caused the IRQ pin to assert. Even when a given
interrupt source is disabled, the status of the condition that
would otherwise cause an interrupt can be determined by
reading the appropriate status register. It is therefore possible
to use the devices without making use of the IRQ pin by polling
the status register(s) to wait for an event, rather than using the
IRQ pin.
Clocks
A 12-MHz crystal (30-ppm or better) is directly connected
between XTAL and GND without the need for external capac-
itors. A digital clock out function is provided, with selectable
output frequencies of 0.75, 1.5, 3, 6, or 12 MHz. This output
may be used to clock an external microcontroller (MCU) or
ASIC. This output is enabled by default, but may be disabled.
Below are the requirements for the crystal to be directly
connected to XTAL pin and GND:
• Nominal Frequency: 12 MHz
• Operating Mode: Fundamental Mode
• Resonance Mode: Parallel Resonant
• Frequency Initial Stability: ±30 ppm
• Series Resistance: <60 ohms
• Load Capacitance: 10 pF
• Drive Level: 10 µW–100 µW
The MCU function features an internal oscillator. The clock
generator provides the 12-MHz and 24-MHz clocks that
remain internal to the microcontroller.
GPIO Interface
The MCU function features up to 15 general-purpose I/O
(GPIO) pins.The I/O pins are grouped into three ports (Port 0
to 2). The pins on Port 0 and Port 1 may each be configured
individually while the pins on Port 2 may only be configured as
a group. Each GPIO port supports high-impedance inputs,
configurable pull up, open drain output, CMOS/TTL inputs,
and CMOS output with up to two pins that support program-
mable drive strength of up to 50-mA sink current. Additionally,
each I/O pin can be used to generate a GPIO interrupt to the
microcontroller. Each GPIO port has its own GPIO interrupt
vector with the exception of GPIO Port 0. GPIO Port 0 has
three dedicated pins that have independent interrupt vectors
(P0.1, P0.3–P0.4).
Power-On Reset/Low-Voltage Detect
The power-on reset circuit detects logic when power is applied
to the device, resets the logic to a known state, and begins
executing instructions at Flash address 0x0000. When power
falls below a programmable trip voltage, it generates reset or
may be configured to generate interrupt. There is a
low-voltage detect circuit that detects when VCC drops below
a programmable trip voltage. It may be configurable to
generate an LVD interrupt to inform the processor about the
low-voltage event. POR and LVD share the same interrupt.
There is not a separate interrupt for each. The Watchdog timer
can be used to ensure the firmware never gets stalled in an
infinite loop.
Timers
The free-running 16-bit timer provides two interrupt sources:
the programmable interval timer with 1-µs resolution and the
1.024-ms outputs. The timer can be used to measure the
duration of an event under firmware control by reading the
timer at the start and at the end of an event, then calculating
the difference between the two values.
Power Management
The operating voltage of the device is 1.8V to 3.6V DC, which
is applied to the VBAT pin. The device can be shut down to a
fully static sleep mode by writing to the FRC END = 1 and END
STATE = 000 bits in the XACT_CFG_ADR register over the
Document #: 001-07611 Rev *B
Page 6 of 73
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