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CYRF7936(2008) View Datasheet(PDF) - Cypress Semiconductor

Part Name
Description
Manufacturer
CYRF7936
(Rev.:2008)
Cypress
Cypress Semiconductor Cypress
CYRF7936 Datasheet PDF : 21 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
CYRF7936
Functional Description
The CYRF7936 CyFi™ Transceiver is a Radio IC designed for low-power embedded wireless applications. Combined with
Cypress’s PSoC programmable system-on-chip and a CyFi network protocol stack, CYRF7936 can be used to implement a
complete CyFi wireless system.
Figure 1. Pin Diagram - CYRF7936 40-Pin QFN
Corner
tabs
XTAL 1
NC 2
VCC 3
NC 4
NC 5
VBAT1 6
VCC 7
VBAT2 8
NC 9
RFBIAS 10
CYRF7936
CyFi Transciever
40 lead QFN
* E- PAD Bottom Side
30 PACTL/ GPIO
29 XOUT/ GPIO
28 MISO/ GPIO
27 MOSI / SDAT
26 IRQ / GPIO
25 SCK
24 SS
23 NC
22 NC
21 NC
Table 1. Pin Description - CYRF7936 40-Pin QFN
Pin Number
13
11
10
30
1
29
Name
RFN
RFP
RFBIAS
PACTL
XTAL
XOUT
25
SCK
28
MISO
27
MOSI
24
SS#
26
IRQ
34
RST
37
40
35
6, 8, 38
3, 7, 16
LVD
VREG
VDD
VBAT(0-2)
VCC
Type
IO
IO
O
IO
I
IO
I
IO
IO
I
IO
I
O
Pwr
Pwr
Pwr
Pwr
Default
Description
I Differential RF signal to and from antenna.
I Differential RF signal to and from antenna.
O RF IO 1.8V reference voltage.
O Control signal for external PA, T/R switch, or GPIO.
I 12 MHz crystal.
O Buffered 0.75, 1.5, 3, 6, or 12 MHz clock, PACTL, or GPIO.
Tri-states in sleep mode (configure as GPIO drive LOW).
I SPI clock.
Z SPI data output pin (Master In Slave Out), or GPIO (in SPI 3-pin mode).
Tri-states when SPI 3PIN = 0 and SS# is deasserted.
I SPI data input pin (Master Out Slave In), or SDAT.
I SPI enable, active LOW assertion. Enables and frames transfers.
O Interrupt output (configurable active HIGH or LOW), or GPIO.
I Device reset. Internal 10 kohm pull down resistor. Active HIGH, typically
connect through a 0.47 μF capacitor to VBAT. Must have RST = 1 event the
first time power is applied to the radio. Otherwise the state of the radio control
registers is unknown.
PMU inductor/diode connection, when used. If not used, connect to GND.
PMU boosted output voltage feedback.
Decoupling pin for 1.8V logic regulator, connect through a 0.47 μF capacitor
to GND.
VBAT = 1.8V to 3.6V. Main supply.
VCC = 2.4V to 3.6V. Typically connected to VREG.
Document #: 001-48013 Rev. **
Page 2 of 21
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