CYRF7936(2008) View Datasheet(PDF) - Cypress Semiconductor

Part Name

Description

Manufacturer

CYRF7936
(Rev.:2008)

2.4 GHz CyFi™ Transceiver

Cypress Semiconductor 

CYRF7936

CRC16 detects the following errors:

■ Any one bit in error.

■ Any two bits in error (irrespective of how far apart, which

column, and so on).

■ Any odd number of bits in error (irrespective of the location).

■ An error burst as wide as the checksum itself.

Figure 2 shows an example packet with SOP, CRC16, and

lengths fields enabled, and Figure 3 shows a standard ACK

packet.

P ream ble

n x 16us

2nd Fram ing

S ym bol*

Figure 2. Example Packet Format

P

SOP 1

SOP 2

Length Payload D ata

CRC 16

1st Fram ing

S ym bol*

P re a m b le

n x 16us

Packet

le n g th

1 Byte

P eriod

Figure 3. Example ACK Packet Format

2 n d F ra m in g

S y m b o l*

*Note:32 or 64us

P

SOP 1

SOP 2

CRC 16

1 s t F ra m in g

S y m b o l*

C R C fie ld fro m

re c e iv e d p a c k e t.

2 B y te p e rio d s

*N o te :3 2 o r 6 4 u s

Packet Buffers

All data transmission and reception use the 16 byte packet

buffers - one for transmission and one for reception.

The transmit buffer allows loading a complete packet of up to 16

bytes of payload data in one burst SPI transaction. This is then

transmitted with no further MCU intervention. Similarly, the

receive buffer allows receiving an entire packet of payload data

up to 16 bytes with no firmware intervention required until the

packet reception is complete.

The CYRF7936 IC supports packets up to 255 bytes. However,

the actual maximum packet length depends on the accuracy of

the clock on each end of the link and the data mode. Interrupts

are provided to allow an MCU to use the transmit and receive

buffers as FIFOs. When transmitting a packet longer than 16

bytes, the MCU can load 16 bytes initially, and add further bytes

to the transmit buffer as transmission of data creates space in

the buffer. Similarly, when receiving packets longer than 16

bytes, the MCU must fetch received data from the FIFO

periodically during packet reception to prevent it from

overflowing.

Auto Transaction Sequencer (ATS)

The CYRF7936 IC provides automated support for transmission

and reception of acknowledged data packets.

When transmitting in transaction mode, the device automatically:

■ starts the crystal and synthesizer

Similarly, when receiving in transaction mode, the device

automatically:

■ waits in receive mode for a valid packet to be received

■ transitions to transmit mode, transmits an ACK packet

■ transitions to the transaction end state (receive mode to await

the next packet, and so on.)

The contents of the packet buffers are not affected by the

transmission or reception of ACK packets.

In each case, the entire packet transaction takes place without

any need for MCU firmware action (as long as packets of 16

bytes or less are used). To transmit data, the MCU must load the

data packet to be transmitted, set the length, and set the TX GO

bit. Similarly, when receiving packets in transaction mode,

firmware must retrieve the fully received packet in response to

an interrupt request indicating reception of a packet.

Data Rates

The CYRF7936 IC supports the following data rates by

combining the PN code lengths and data transmission modes

described in the previous sections:

■ 1000 kbps (GFSK)

■ 250 kbps (32 chip 8DR)

■ 125 kbps (64 chip 8DR)

■ enters transmit mode

■ transmits the packet in the transmit buffer

■ transitions to receive mode and waits for an ACK packet

■ transitions to the transaction end state when an ACK packet is

received or a timeout period expires

Document #: 001-48013 Rev. **

Page 4 of 21

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