CYRF7936(2008) View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
CYRF7936 Datasheet PDF : 21 Pages
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CYRF7936
Functional Block Overview
2.4 GHz CyFi Radio Modem
The CyFi radio Modem is a dual conversion low IF architecture
optimized for power, range, and robustness. The CyFi radio
modem employs channel-matched filters to achieve high perfor-
mance in the presence of interference. An integrated Power
Amplifier (PA) provides up to +4 dBm transmit power, with an
output power control range of 34 dB in seven steps. The supply
current of the device is reduced as the RF output power is
reduced.
Table 2. Internal PA Output Power Step Table
PA Setting
Typical Output Power (dBm)
7
+4
6
0
5
–5
4
–13
3
–18
2
–24
1
–30
0
–35
Frequency Synthesizer
Before transmission or reception may begin, the frequency
synthesizer must settle. The settling time varies depending on
channel; 25 fast channels are provided with a maximum settling
time of 100 μs.
The ‘fast channels’ (less than 100 μs settling time) are every third
channel, starting at 0 up to and including 72 (for example, 0, 3,
6, 9 …. 69, 72).
Baseband and Framer
The baseband and framer blocks provide the DSSS encoding
and decoding, SOP generation and reception, CRC16
generation and checking, and EOP detection and length field.
Packet Buffers and Radio Configuration Registers
Packet data and configuration registers are accessed through
the SPI interface. All configuration registers are directly
addressed through the address field in the SPI packet. Configu-
ration registers allow configuration of DSSS PN codes, data rate,
operating mode, interrupt masks, interrupt status, and so on.
SPI Interface
The CYRF7936 IC has an SPI interface supporting
communication between an application MCU and one or more
slave devices (including the CYRF7936). The SPI interface
supports single-byte and multi-byte serial transfers using either
4-pin or 3-pin interfacing. The SPI communications interface
consists of Slave Select (SS#), Serial Clock (SCK), Master
Out-Slave In (MOSI), Master In-Slave Out (MISO), or Serial Data
(SDAT).
SPI communication may be described as the following:
■ Command Direction (bit 7) = ‘1’ enables SPI write transaction.
When it equals a ‘0’, it enables SPI read transactions.
■ Command Increment (bit 6) = ‘1’ enables SPI auto address
increment. When set, the address field automatically
increments at the end of each data byte in a burst access.
Otherwise the same address is accessed.
■ Six bits of address
■ Eight bits of data
The device receives SCK from an application MCU on the SCK
pin. Data from the application MCU is shifted in on the MOSI pin.
Data to the application MCU is shifted out on the MISO pin. The
active LOW Slave Select (SS#) pin must be asserted to initiate
an SPI transfer.
The application MCU can initiate SPI data transfers using a
multi-byte transaction. The first byte is the Command/Address
byte, and the following bytes are the data bytes shown in
Figure 4 through Figure 7 on page 6.
The SPI communications interface has a burst mechanism,
where the first byte can be followed by as many data bytes as
required. A burst transaction is terminated by deasserting the
slave select (SS# = 1).
The SPI communications interface single read and burst read
sequences are shown in Figure 5 and Figure 6 on page 6,
respectively.
The SPI communications interface single write and burst write
sequences are shown in Figure 7 and Figure 8 on page 6,
respectively.
This interface may be optionally operated in a 3-pin mode with
the MISO and MOSI functions combined in a single bidirectional
data pin (SDAT). When using 3-pin mode, user firmware must
ensure that the MOSI pin on the MCU is in a high impedance
state except when MOSI is actively transmitting data.
The device registers may be written to or read from one byte at
a time, or several sequential register locations may be written or
read in a single SPI transaction using incrementing burst mode.
In addition to single byte configuration registers, the device
includes register files. Register files are FIFOs written to and
read from using nonincrementing burst SPI transactions.
The IRQ pin function may be optionally multiplexed onto the
MOSI pin. When this option is enabled, the IRQ function is not
available while the SS# pin is LOW. When using this configu-
ration, user firmware must ensure that the MOSI pin on the MCU
is in a high impedance state whenever the SS# pin is HIGH.
The SPI interface is not dependent on the internal 12 MHz clock.
Registers may therefore be read from or written to when the
device is in sleep mode, and the 12 MHz oscillator disabled.
The SPI interface and the IRQ and RST pins have a separate
voltage reference pin (VIO). This enables the device to interface
directly to MCUs operating at voltages below the CYRF7936 IC
supply voltage.
Document #: 001-48013 Rev. **
Page 5 of 21
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