MT48LC128M4A2(2002) View Datasheet(PDF) - Micron Technology
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Description
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MT48LC128M4A2 Datasheet PDF : 55 Pages
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READs
READ bursts are initiated with a READ command, as
shown in Figure 5.
The starting column and bank addresses are provided
with the READ command, and auto precharge is either
enabled or disabled for that burst access. If auto precharge
is enabled, the row being accessed is precharged at the
completion of the burst. For the generic READ com-
mands used in the following illustrations, auto precharge
is disabled.
During READ bursts, the valid data-out element from
the starting column address will be available following
the CAS latency after the READ command. Each subse-
quent data-out element will be valid by the next positive
clock edge. Figure 6 shows general timing for each pos-
sible CAS latency setting.
CLK
CKE HIGH
CS#
RAS#
CAS#
WE#
A0-A9, A11, A12: x4
A0-A9, A11: x8
A0-A9: x16
A12: x4
A11, A12: x8
A9, A11, A12: x16
A10
BA0,1
COLUMN
ADDRESS
ENABLE AUTO PRECHARGE
DISABLE AUTO PRECHARGE
BANK
ADDRESS
Figure 5
READ Command
ADVANCE
512Mb: x4, x8, x16
SDRAM
Upon completion of a burst, assuming no other com-
mands have been initiated, the DQs will go High-Z. A full-
page burst will continue until terminated. (At the end of
the page, it will wrap to the start address and continue.)
Data from any READ burst may be truncated with a
subsequent READ command, and data from a fixed-length
READ burst may be immediately followed by data from a
READ command. In either case, a continuous flow of data
can be maintained. The first data element from the new
burst follows either the last element of a completed burst
or the last desired data element of a longer burst that is
being truncated. The new READ command should be
issued x cycles before the clock edge at which the last
desired data element is valid, where x equals the CAS
latency minus one. This is shown in Figure 7 for CAS
T0
T1
T2
T3
CLK
COMMAND
DQ
READ
NOP
tLZ
tAC
CAS Latency = 2
NOP
tOH
DOUT
CLK
COMMAND
T0
READ
DQ
T1
T2
NOP
NOP
tLZ
tAC
CAS Latency = 3
Figure 6
CAS Latency
T3
T4
NOP
tOH
DOUT
DON’T CARE
UNDEFINED
512Mb: x4, x8, x16 SDRAM
512MSDRAM_D.p65 – Rev. D; Pub 1/02
15
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©2000, Micron Technology, Inc.
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