MT48LC128M4A2 View Datasheet(PDF) - Micron Technology
Part Name
Description
Manufacturer
MT48LC128M4A2 Datasheet PDF : 68 Pages
| |||
512Mb: x4, x8, x16 SDRAM
General Description
Table 3: Pin Descriptions
Pin
Numbers
38
Symbols
CLK
37
CKE
19
CS#
18, 17, 16
39
15, 39
RAS#,
CAS#, WE#
x4, x8:
DQM
x16:
DQML,
DQMH
20, 21 BA0, BA1
23–26, 29–
34, 22, 35,
36
A0–A12
2, 4, 5, 7, 8,
10, 11, 13,
42, 44, 45,
47, 48, 50,
51, 53
DQ0–DQ15
2, 5, 8, 11, DQ0–DQ7
44, 47, 50,
53
5, 11, 44, DQ0–DQ3
50
40
NC
3, 9, 43, 49 VDDQ
6, 12, 46,
52
VSSQ
1, 14, 27
VDD
28, 41, 54
VSS
Type
Input
Input
Input
Input
Input
Input
Input
x16: I/O
x8: I/O
x4: I/O
–
Supply
Supply
Supply
Supply
Description
Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on
the positive edge of CLK. CLK also increments the internal burst counter and
controls the output registers.
Clock enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal.
Deactivating the clock provides PRECHARGE power-down and SELF REFRESH
operation (all banks idle), ACTIVE power-down (row active in any bank), or CLOCK
SUSPEND operation (burst/access in progress). CKE is synchronous except after the
device enters power-down and self refresh modes, where CKE becomes
asynchronous until after exiting the same mode. The input buffers, including CLK,
are disabled during power-down and self refresh modes, providing low standby
power. CKE may be tied HIGH.
Chip select: CS# enables (registered LOW) and disables (registered HIGH) the
command decoder. All commands are masked when CS# is registered HIGH. CS#
provides for external bank selection on systems with multiple banks. CS# is
considered part of the command code.
Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command
being entered.
Input/output mask: DQM is an input mask signal for write accesses and an output
enable signal for read accesses. Input data is masked when DQM is sampled HIGH
during a WRITE cycle. The output buffers are placed in a High-Z state (two-clock
latency) when DQM is sampled HIGH during a READ cycle. On the x4 and x8, DQML
(Pin 15) is a NC and DQMH is DQM. On the x16, DQML corresponds to DQ0–DQ7,
and DQMH corresponds to DQ8–DQ15. DQML and DQMH are considered same
state when referenced as DQM.
Bank address inputs: BA0 and BA1 define to which bank the ACTIVE, READ, WRITE,
or PRECHARGE command is being applied.
Address inputs: A0–A12 are sampled during the ACTIVE command (row-address
A0–A12) and READ/WRITE command (column-address A0–A9, A11, A12 [x4]; A0–
A9, A11 [x8]; A0–A9 [x16]; with A10 defining auto precharge) to select one location
out of the memory array in the respective bank. A10 is sampled during a
PRECHARGE command to determine whether all banks are to be precharged (A10
[HIGH]) or bank selected by (A10 [LOW]). The address inputs also provide the op-
code during a LOAD MODE REGISTER command.
Data input/output: Data bus for x16 (4, 7, 10, 13, 15, 42, 45, 48, and 51 are NCs for
x8; 2, 4, 7, 8, 10, 13, 15, 42, 45, 47, 48, 51, and 53 are NCs for x4).
Data input/output: Data bus for x8 (2, 8, 47, and 53 are NCs for x4).
Data input/output: Data bus for x4.
No connect: This pin should be left unconnected.
DQ power: Isolated DQ power to the die for improved noise immunity.
DQ ground: Isolated DQ ground to the die for improved noise immunity.
Power supply: +3.3V ±0.3V.
Ground.
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
10
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000 Micron Technology, Inc. All rights reserved.
Share Link: 