PEEL22LV10AZ View Datasheet(PDF) - International Cmos Technology

Part Name

Description

Manufacturer

PEEL22LV10AZ

CMOS Programmable Electrically Erasable Logic Device

International Cmos Technology 

Commercial/Industrial

PEEL™ 22LV10AZ-25 / I-35

CMOS Programmable Electrically Erasable Logic Device

Features

• Low Voltage, Ultra Low Power Operation

- Vcc = 2.7 to 3.6 V

- Icc = 5 µA (typical) at standby

- Icc = 1.5 mA (typical) at 1 MHz

- Meets JEDEC LV Interface Spec (JESD8-B)

- 5 Volt tolerant inputs and I/O’s

• CMOS Electrically Erasable Technology

- Superior factory testing

- Reprogrammable in plastic package

- Reduces retrofit and development costs

• Application Versatility

- Replaces random logic

- Super set of standard PLDs

- Pin and JEDEC compatible with 22V10

- Ideal for battery powered systems

- Replaces expensive oscillators

General Description

The PEEL22LV10AZ is a Programmable Electrically

Erasable Logic (PEEL) SPLD (Simple Programmable

Logic Device) that operates over the supply voltage

range of 2.7V-3.6V and features ultra-low, automatic

"zero" power-down operation. The PEEL22LV10AZ is

logically and functionally similar to ICT's 5V

PEEL22CV10A and PEEL22CV10AZ. The "zero power"

(25 µA max. ICC) power-down mode makes the

PEEL22LV10AZ ideal for a broad range of battery-

powered portable equipment applications, from hand-

held meters to PCMCIA modems. EE-

reprogrammability provides both the convenience of

product fast reprogramming for product development

and quick personalization in manufacturing, including

Engineering Change Orders.

• Architectural Flexibility

- Enhanced architecture fits in more logic

- 133 product terms x 44 input AND array

- 12 inputs and 10 I/O pins

- 12 possible macrocell configurations

- Asynchronous clear, synchronous preset

- Independent output enables

- Programmable clock; pin 1 or p-term

- Programmable clock polarity

- 24-Pin DIP/SOIC/TSSOP and 28 Pin PLCC

- Schmitt triggers on clock and data inputs

• Schmitt Trigger Inputs

- Eliminates external Schmitt trigger devices

- Ideal for encoder designs

The differences between the PEEL22LV10AZ and

PEEL22CV10A include the addition of programmable

clock polarity, p-term clock, and Schmitt trigger input

buffers on all inputs, including the clock. Schmitt trigger

inputs allow direct input of slow signals such as

biomedical and sine waves or clocks. Like the

PEEL22CV10A, the PEEL22LV10AZ is a pin and

JEDEC compatible, logical superset of the industry

standard PAL22V10 SPLD Figure 1. The

PEEL22LV10AZ provides additional architectural

features that allow more logic to be incorporated into

the design. The PEEL22LV10AZ architecture allows it

to replace over twenty standard 24-pin DIP, SOIC,

TSSOP

and

PLCC

packages.

Figure 1 - Pin Configuration

I/CLK 1 24 VCC I/CLK

1

I 2 23 I/O

I

2

I 3 22 I/O

I

3

I 4 21 I/O

I

4

I 5 20 I/O

I

5

I 6 19 I/O

I

6

I 7 18 I/O

I

7

I 8 17 I/O

I

8

I 9 16 I/O

I

9

I 10 15 I/O

I

10

I 11 14 I/O

I

11

GND 12 13 I

GND

12

DIP

24

VCC

23

I/O

22

I/O

21

I/O

20

I/O

19

I/O

18

I/O

17

I/O

16

I/O

15

I/O

14

I/O

13

I

TSSOP

I

4 3 2 1 28 27 26

5

25

I/O

I6

24 I/O

I/CLK

I

1

2

I7

23 I/O

I3

NC 8

22 NC

I4

I9

21 I/O

I 10

20 I/O

I 11

19 I/O

12 1314 15 1617 18

I5

I6

I7

I8

I9

I

10

I

11

GND 12

PLCC

24 VCC

23 I/O

22 I/O

21 I/O

20 I/O

19 I/O

18 I/O

17 I/O

16 I/O

15 I/O

14 I/O

13 I

SOIC

Figure 2 - Block Diagram

CLK MUX (Optional)

I/CLK

SP

I

AC

I

PEEL TM

I

"AND"

OE

I

ARRAY

I

I/O

I

MACRO

I/O

I

133 Terms

CELL

I/O

I

X

I

44 Inputs

I/O

I/O

I/O

I

I/O

I

I/O

I/O

I/O

SP = SYNCHRONOUS PRESET

AC = ASYNCHRONOUS CLEAR

OE = OUTPUT ENABLE

1

04-02-037D

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