DS1205S View Datasheet(PDF) - Dallas Semiconductor -> Maxim Integrated

Part Name

Description

Manufacturer

DS1205S

MultiKey Chip

Dallas Semiconductor -> Maxim Integrated 

DS1205S

MOVE BLOCK Figure 12

WRITE MOVE BLOCK IN

COMMAND WORD

WRITE 64–BIT BLOCK

SELECTOR CODE

TO DS1205

WRITE 64–BIT

PASSWORD

OF DESTINATION

SUBKEY

IS DATA =

NO

PARTITION

PASSWORD?

YES

TERMINATE

TRANSACTION

TRANSFER SPECIFIED

* SCRATCHPAD DATA BLOCKS

TO SPECIFIED PARTITION

3-WIRE BUS

The 3-wire bus is comprised of three signals. These are

the RST (reset) signal, the CLK (clock) signal, and the

DQ (data) signal. All data transfers are initiated by driv-

ing the RST input high. The RST signal provides a meth-

od of terminating a data transfer.

A clock cycle is a sequence of a falling edge followed by

a rising edge. For data inputs, the data must be valid

during the rising edge of a clock cycle. Command bits

and data bits are input on the rising edge of the clock and

data bits are output on the falling edge of the clock. All

data transfers terminate if RST is low and the DQ pin

goes to a high impedance state. When data transfers to

the DS1205S are terminated by the RST signal going

low, the transition of the RST going low must occur dur-

ing a high level of the CLK signal. Failure to ensure that

the CLK signal is high will result in the corruption of the

last bit transferred. Data transfers are illustrated in

Figure 13 and Figure 14 for normal modes of operation.

ERASE ALL

* SCRATCHPAD MEMORY

TERMINATE TRANSACTION

*TRANSPARENT TO USER

021798 8/17

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