DS1205S View Datasheet(PDF) - Dallas Semiconductor -> Maxim Integrated

Part Name

Description

Manufacturer

DS1205S

MultiKey Chip

Dallas Semiconductor -> Maxim Integrated 

WRITE DATA TIMING DIAGRAM Figure 13

RESET

tCC

tCL

tR

tF

CLOCK

tDC

DATA

INPUT/OUTPUT

R/W

tCDH

tCH

R/W

R/W

READ DATA TIMING DIAGRAM Figure 14

RESET

CLOCK

tCC

tDC

R/W

tCDD

DS1205S

tCWH

tCCH

tCWH

tCDZ

1-WIRE PROTOCOL

The 1-wire protocol defines the system as a single bus

master system with single or multiple slaves. In all

instances, the DS1205S is a slave. The bus master is

typically a microcontroller. The discussion of this proto-

col is broken down into two topics: hardware configura-

tion and transaction sequence.

Hardware Configuration

The 1-wire bus has only a single line by definition; it is

important that each device on the bus be able to drive it

at the appropriate time. To facilitate this, each device at-

tached to the 1-wire bus must have open drain connec-

tions. The DS1205S is an open drain part with an inter-

nal circuit equivalent to that shown in Figure 15. Ideally,

the bus master should also be open drain; but if this is

not feasible, two standard TTL pins can be tied together,

one as an output and one as an input. When using a bus

master with an open drain port, the bus requires a pull-

up resistor at the master end of the bus. The system bus

master circuit should be equivalent to the one shown in

Figure 16. The value of the pull-up resistor should be

greater than 5K ohms. If the pull-up value is less, the bus

may not be pulled to an adequately low state (< 0.6

volts).

The idle state for the 1-wire bus is high. If, for any rea-

son, a transaction needs to be suspended, the bus

MUST be left in the idle state if the transaction is to re-

sume. If this does not occur and the bus is left for more

than 560 µS, all components on the bus will be reset.

021798 9/17

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