DS17285(1998) View Datasheet(PDF) - Dallas Semiconductor -> Maxim Integrated

Part Name

Description

Manufacturer

DS17285
(Rev.:1998)

3 Volt/5 Volt Real Time Clock

Dallas Semiconductor -> Maxim Integrated 

DS17285/DS17287

The third method uses a periodic interrupt to determine

if an update cycle is in progress. The UIP bit in Register

A is set high between the setting of the PF bit in Register

C (see Figure 3). Periodic interrupts that occur at a rate

of greater than tBUC allow valid time and date informa-

tion to be reached at each occurrence of the periodic

interrupt. The reads should be complete within

(tPI / 2+tBUC) to ensure that data is not read during the

update cycle.

UPDATE–ENDED AND PERIODIC INTERRUPT RELATIONSHIP Figure 3

UIP BIT IN

REGISTER A

tBUC

UF BIT IN

REGISTER C

PF BIT IN

REGISTER C

ÎÎÎÎÎÎ

tPI

ÎÎÎÎÎÎtPI/2

tPI/2

tPI = PERIODIC INTERRUPT TIME INTERNAL PER TABLE 1

tBUC = DELAY TIME BEFORE UPDATE CYCLE = 244 µs

REGISTER A

MSB

BIT 7 BIT 6 BIT 5

UIP DV2 DV1

BIT 4

DV0

BIT 3

RS3

BIT 2

RS2

BIT 1

RS1

LSB

BIT 0

RS0

UIP – The Update In Progress (UIP) bit is a status flag

that can be monitored. When the UIP bit is a one, the

update transfer will soon occur. When UIP is a zero, the

update transfer will not occur for at least 244 µs. The

time, calendar, and alarm information in RAM is fully

available for access when the UIP bit is zero. The UIP

bit is read only. Writing the SET bit in Register B to a one

inhibits any update transfer and clears the UIP status

bit.

DV2, DV1, DV0 – These bits are defined as follows:

DV2 =

DV1 =

DV0 =

Countdown Chain

1 – resets countdown chain only if DV1=1

0 – countdown chain enabled

Oscillator Enable

0 – oscillator off

1 – oscillator on, VCC power–up state

Bank Select

0 – original bank

1 – extended registers

A pattern of 01X is the only combination of bits that will

turn the oscillator on and allow the RTC to keep time. A

pattern of 11X will enable the oscillator but holds the

countdown chain in reset. The next update will occur at

500 ms after a pattern of 01X is written to DV2, DV1, and

DV0.

RS3, RS2, RS1, RS0 – These four rate–selection bits

select one of the 13 taps on the 15–stage divider or dis-

able the divider output. The tap selected can be used to

generate an output square wave (SQW pin) and/or a

periodic interrupt. The user can do one of the following

Enable the interrupt with the PIE bit;

Enable the SQW output pin with the SQWE or E32K

bits;

Enable both at the same time and the same rate; or

Enable neither.

Table 2 lists the periodic interrupt rates and the square

wave frequencies that can be chosen with the RS bits.

030598 10/32

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