DS17285(1998) View Datasheet(PDF) - Dallas Semiconductor -> Maxim Integrated
Part Name
Description
Manufacturer
DS17285 Datasheet PDF : 32 Pages
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DS17285/DS17287
PIN DESCRIPTION
X1
– Crystal Input
X2
– Crystal Output
RCLR
– RAM Clear Input
AD0-AD7 – Mux’ed Address/Data Bus
PWR
– Power–on Interrupt Output (open drain)
KS
– Kickstart Input
CS
– RTC Chip Select Input
ALE
– RTC Address Strobe
WR
– RTC Write Data Strobe
RD
– RTC Read Data Strobe
IRQ
– Interrupt Request Output (open drain)
SQW
– Square Wave Output
VCC
GND
– +3 or +5 Volt Main Supply
– Ground
VBAT
VBAUX
NC
– Battery + Supply
– Auxiliary Battery Supply
– No Connection
DESCRIPTION
The DS17285/DS17287 is a real time clock (RTC)
designed as a successor to the industry standard
DS1285, DS1385, DS1485, DS1585, and DS1685 PC
real time clocks. This device provides the industry stan-
dard DS1285 clock function with either +3.0 or +5.0 volt
operation . The DS17285 also incorporates a number of
enhanced features including a silicon serial number,
power on/off control circuitry, 114 bytes of user
NV SRAM plus 2K bytes of additional NVRAM, and
32.768 KHz output for sustaining power management
activities.
The DS17285/DS17287 power control circuitry allows
the system to be powered on via an external stimulus,
such as a keyboard or by a time and date (wake up)
alarm. The PWR output pin can be triggered by one or
either of these events, and can be used to turn on an
external power supply. The PWR pin is under software
control, so that when a task is complete, the system
power can then be shut down.
The DS17285 is a clock/calendar chip with the features
described above. An external crystal and battery are
the only components required to maintain time–of–day
and memory status in the absence of power. The
DS17287 incorporates the DS17285 chip, a 32.768
KHz crystal, and a lithium battery in a complete, self–
contained timekeeping module. The entire unit is fully
tested at Dallas Semiconductor such that a minimum of
10 years of timekeeping and data retention in the
absence of VCC is guaranteed.
OPERATION
The block diagram in Figure 1 shows the pin connec-
tions with the major internal functions of the
DS17285/DS17287. The following paragraphs
describe the function of each pin.
SIGNAL DESCRIPTIONS
GND, VCC – DC power is provided to the device on
these pins. VCC is the +3 volt or +5 volt input.
SQW (Square Wave Output) – The SQW pin will pro-
vide a 32 KHz square wave output, tREC, after a pow-
er–up condition has been detected. This condition sets
the following bits, enabling the 32 KHz output; DV1=1,
and E32K=1. A square wave will be output on this pin if
either SQWE=1 or E32K=1. If E32K=1, then 32 KHz will
be output regardless of the other control bits. If E32K=0,
then the output frequency is dependent on the control
bits in register A. The SQW pin can output a signal from
one of 13 taps provided by the 15 internal divider stages
of the real time clock. The frequency of the SQW pin can
be changed by programming Register A as shown in
Table 2. The SQW signal can be turned on and off using
the SQWE bit in register B or the E32K bit in extended
register 4Bh. A 32 KHz SQW signal is output when the
Enable 32 KHz (E32K) bit in extended register 4Bh is a
logic one, and VCC is above VPF. A 32 KHz square wave
is also available when VCC is less than VPF if E32K=1,
ABE=1, and voltage is applied to the VBAUX pin.
AD0–AD7 (Multiplexed Bidirectional Address/Data
Bus) – Multiplexed buses save pins because address
information and data information time share the same
signal paths. The addresses are present during the first
portion of the bus cycle and the same pins and signal
paths are used for data in the second portion of the
cycle. Address/data multiplexing does not slow the
access time of the DS17285 since the bus change from
address to data occurs during the internal RAM access
time. Addresses must be valid prior to the latter portion
of ALE, at which time the DS17285/DS17287 latches
the address. Valid write data must be present and held
stable during the latter portion of the WR pulse. In a read
cycle the DS17285/DS17287 outputs 8 bits of data dur-
ing the latter portion of the RD pulse. The read cycle is
terminated and the bus returns to a high impedance
state as RD transitions high. The address/data bus also
serves as a bidirectional data path for the external
extended RAM.
030598 2/32
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