DS17285(1998) View Datasheet(PDF) - Dallas Semiconductor -> Maxim Integrated

Part Name

Description

Manufacturer

DS17285
(Rev.:1998)

3 Volt/5 Volt Real Time Clock

Dallas Semiconductor -> Maxim Integrated 

DS17285/DS17287

ALE (RTC Address Strobe Input; active high) – A

pulse on the address strobe pin serves to demultiplex

the bus. The falling edge of ALE causes the RTC

address to be latched within the DS17285/DS17287.

RD (RTC Read Input; active low) – RD identifies the

time period when the DS17285/DS17287 drives the bus

with RTC read data. The RD signal is an enable signal

for the output buffers of the clock.

WR (RTC Write Input; active low) – The WR signal is

an active low signal. The WR signal defines the time

period during which data is written to the addressed reg-

ister.

CS (RTC Chip Select Input; active low) – The Chip

Select signal must be asserted low during a bus cycle

for the DS17285/DS17287 to be accessed. CS must be

kept in the active state during RD and WR timing. Bus

cycles which take place with ALE asserted but without

asserting CS will latch addresses. However, no data

transfer will occur.

IRQ (Interrupt Request Output; open drain, active

low) – The IRQ pin is an active low output of the

DS17285/DS17287 that can be tied to the interrupt input

of a processor. The IRQ output remains low as long as

the status bit causing the interrupt is present and the

corresponding interrupt-enable bit is set. To clear the

IRQ pin, the application software must clear all enabled

flag bits contributing to IRQ’s active state.

When no interrupt conditions are present, the IRQ level

is in the high impedance state. Multiple interrupting

devices can be connected to an IRQ bus. The IRQ pin

is an open drain output and requires an external pull-up

resistor.

PWR (Power On Output; open drain, active low) –

The PWR pin is intended for use as an on/off control for

the system power. With VCC voltage removed from the

DS17285/DS17287, PWR may be automatically acti-

vated from a Kickstart input via the KS pin or from a

Wake Up interrupt. Once the system is powered on, the

state of PWR can be controlled via bits in the Dallas reg-

isters.

KS (Kickstart Input; active low) – When VCC is

removed from the DS17285/DS17287, the system can

be powered on in response to an active low transition on

the KS pin, as might be generated from a key closure.

VBAUX must be present and Auxiliary Battery Enable bit

(ABE) must be set to 1 if the kickstart function is used,

and the KS pin must be pulled up to the VBAUX supply.

While VCC is applied, the KS pin can be used as an inter-

rupt input.

RCLR (RAM Clear Input; active low) – If enabled by

software, taking RCLR low will result in the clearing of

the 114 bytes of user RAM. When enabled, RCLR can

be activated whether or not VCC is present.

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