DS17285(1998) View Datasheet(PDF) - Dallas Semiconductor -> Maxim Integrated
Part Name
Description
Manufacturer
DS17285 Datasheet PDF : 32 Pages
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DS17285/DS17287
a result, there are cases where the software should
clear these earlier generated interrupts before first
enabling new interrupts.
When an interrupt event occurs, the relating flag bit is
set to a logic 1 in Register C or in Extended Register 4A.
These flag bits are set regardless of the setting of the
corresponding enable bit located either in Register B or
in Extended Register 4B. The flag bits can be used in a
polling mode without enabling the corresponding
enable bits.
However, care should be taken when using the flag bits
of Register C as they are automatically cleared to 0
immediately after they are read. Double latching is
implemented on these bits so that bits which are set
remain stable throughout the read cycle. All bits which
were set are cleared when read and new interrupts
which are pending during the read cycle are held until
after the cycle is completed. One, two, or three bits can
be set when reading Register C. Each utilized flag bit
should be examined when read to ensure that no inter-
rupts are lost.
The flag bits in Extended Register 4A are not automati-
cally cleared following a read. Instead, each flag bit can
be cleared to 0 only by writing 0 to that bit.
When using the flag bits with fully enabled interrupts, the
IRQ line will be driven low when an interrupt flag bit is set
and its corresponding enable bit is also set. IRQ will be
held low as long as at least one of the six possible interrupt
sources has it s flag and enable bits both set. The IRQF
bit in Register C is a 1 whenever the IRQ pin is being
driven low as a result of one of the six possible active
sources. Therefore, determination that the
DS17285/DS17287 initiated an interrupt is accomplished
by reading Register C and finding IRQF=1. IRQF will
remain set until all enabled interrupt flag bits are
cleared to 0.
SQUARE WAVE OUTPUT SELECTION
The SQW pin can be programmed to output a variety of
frequencies divided down from the 32.768 KHz crystal
tied to X1 and X2. The square wave output is enabled
and disabled via the SQWE bit in Register B or the E32K
bit in extended register 4Bh. If the square wave is
enabled (SQWE=1 or E32K=1), then the output fre-
quency will be determined by the settings of the E32K bit
in Extended Register 4Bh and by the RS3–0 bits in Reg-
ister A. If E32K=1, then a 32.768 KHz square wave will
be output on the SQW pin regardless of the settings of
RS3–0 and SQWE.
If E32K = 0, then the square wave output frequency is
determined by the RS3–0 bits. These bits control a
1–of–15 decoder which selects one of thirteen taps that
divide the 32.768 KHz frequency. The RS3–0 bits
establish the SQW output frequency as shown in
Table 2. In addition, RS3–0 bits control the periodic
interrupt selection as described below.
If E32K=1, and the Auxiliary Battery Enable bit (ABE,
bank 1; register 04BH) is enabled, and voltage is
applied to VBAUX then the 32 KHz square wave output
signal will be output on the SQW pin in the absence of
VCC. This facility is provided to clock external power
management circuitry. If any of the above requirements
are not met, no square wave output signal will be gener-
ated on the SQW pin in the absence of VCC.
A pattern of 01X in the DV2, DV1, and DV0, bits respec-
tively, will turn the oscillator on and enable the count-
down chain. Note that this is different than the DS1287,
which required a pattern of 010 in these bits. DV0 is now
a “don’t care” because it is used for selection between
register banks 0 and 1.
A pattern of 11X will turn the oscillator on, but the oscilla-
tor’s countdown chain will be held in reset, as it was in
the DS1287. Any other bit combination for DV2 and
DV1 will keep the oscillator off.
PERIODIC INTERRUPT SELECTION
The periodic interrupt will cause the IRQ pin to go to an
active state from once every 500 ms to once every
122 µs. This function is separate from the alarm inter-
rupt which can be output from once per second to once
per day. The periodic interrupt rate is selected using the
same RS3–0 bits in Register A which select the square
wave frequency (see Table 2). Changing the bits affects
both the square wave frequency and the periodic inter-
rupt output. However, each function has a separate
enable bit in Register B. The SQWE and E32K bits con-
trol the square wave output. Similarly, the periodic inter-
rupt is enabled by the PIE bit in Register B. The periodic
interrupt can be used with software counters to measure
inputs, create output intervals, or await the next needed
software function.
030598 8/32
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