DS17285(1998) View Datasheet(PDF) - Dallas Semiconductor -> Maxim Integrated
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Description
Manufacturer
DS17285 Datasheet PDF : 32 Pages
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DS17285/DS17287
UPDATE CYCLE
The Serialized RTC executes an update cycle once per
second regardless of the SET bit in Register B. When
the SET bit in Register B is set to one, the user copy of
the double buffered time, calendar, alarm and elapsed
time byte is frozen and will not update as the time incre-
ments. However, the time countdown chain continues to
update the internal copy of the buffer. This feature
allows the time to maintain accuracy independent of
reading or writing the time, calendar, and alarm buffers
and also guarantees that time and calendar information
is consistent. The update cycle also compares each
alarm byte with the corresponding time byte and issues
an alarm if a match or if a “don’t care” code is present in
all alarm locations.
There are three methods that can handle access of the
real-time clock that avoid any possibility of accessing
inconsistent time and calendar data. The first method
uses the update–ended interrupt. If enabled, an inter-
rupt occurs after every up date cycle that indicates that
over 999 ms are available to read valid time and date
information. If this interrupt is used, the IRQF bit in Reg-
ister C should be cleared before leaving the interrupt
routine.
A second method uses the update–in–progress bit
(UIP) in Register A to determine if the update cycle is in
progress. The UIP bit will pulse once per second. After
the UIP bit goes high, the update transfer occurs 244 µs
later. If a low is read on the UIP bit, the user has at least
244 µs before the time/calendar data will be changed.
Therefore, the user should avoid interrupt service rou-
tines that would cause the time needed to read valid
time/calendar data to exceed 244 µs.
PERIODIC INTERRUPT RATE AND SQUARE WAVE OUTPUT FREQUENCY Table 2
EXT. REG. B
E32K
SELECT BITS REGISTER A
RS3
RS2
RS1
RS0
tPI PERIODIC
INTERRUPT RATE
SQW OUTPUT
FREQUENCY
0
0
0
0
0
None
None
0
0
0
0
1
3.90625 ms
256 Hz
0
0
0
1
0
7.8125 ms
0
0
0
1
1
122.070 µs
0
0
1
0
0
244.141 µs
0
0
1
0
1
488.281 µs
0
0
1
1
0
976.5625 µs
0
0
1
1
1
1.953125 ms
128 Hz
8.192 KHz
4.096 KHz
2.048 KHz
1.024 KHz
512 Hz
0
1
0
0
0
3.90625 ms
256 Hz
0
1
0
0
1
7.8125 ms
128 Hz
0
1
0
1
0
15.625 ms
64 Hz
0
1
0
1
1
31.25 ms
32 Hz
0
1
1
0
0
62.5 ms
16 Hz
0
1
1
0
1
125 ms
8 Hz
0
1
1
1
0
250 ms
4 Hz
0
1
1
1
1
500 ms
2 Hz
1
X
X
X
X
*
32.768 KHz
*RS3-RS0 determine periodic interrupt rates as listed for E32K=0.
030598 9/32
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