DS2182AQ View Datasheet(PDF) - Dallas Semiconductor -> Maxim Integrated
Part Name
Description
Manufacturer
DS2182AQ Datasheet PDF : 26 Pages
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DS2182A
Table 1. PIN DESCRIPTION
PIN SYMBOL TYPE
FUNCTION
1
INT
O
Receive Alarm Interrupt. Flags host controller during alarm conditions.
Active low; open-drain output.
2
SDI
I Serial Data In. Data for on-board registers. Sampled on rising edge of SCLK.
3
4
5
6, 13
7
SDO
CS
SCLK
N.C.
RYEL
8
RLINK
Serial Data Out. Control and status information from on-board registers.
O Updated on falling edge of SCLK; tri-stated during serial port write or when
CS is high.
I Chip Select. Must be low to read or write the serial port.
I Serial Data Clock. Used to read or write the serial port registers.
—
No Connect. No internal connection. This pin can be connected to either VSS
or VDD, or it can be floated.
O
Receive Yellow Alarm. Transitions high when a yellow alarm detected; goes
low when the alarm clears.
Receive Link Data. Updated with extracted FDL data one RCLK before start
O of odd frames (193E) and held until next update. Updated with extracted S-bit
data one RCLK before start of even frames (193S) and held until next update.
9
RLCLK
O Receive Link Clock. 4kHz demand clock for RLINK
10
RCLK
11 RCHCLK
12
RSER
15 RFSYNC
16 RMSYNC
17 RABCD
18 RSIGFR
19 RSIGSEL
21
RST
22
RPOS
23
RNEG
24
RCL
25
RBV
26 RFER
27
RLOS
I Receive Clock. 1.544MHz primary clock
O
Receive Channel Clock. 192kHz clock; identifies timeslot (channel)
boundaries
O
Receive Serial Data. Received NRZ serial data; updated on rising edges of
RCLK
O
Receive Frame Sync. Extracted 8kHz clock, one RCLK wide; F-bit position
in each frame
O
Receive Multiframe Sync. Extracted multiframe sync; positive-going edge
indicates start of multiframe; 50% duty cycle
Receive ABCD Signaling. Extracted signaling data output; valid for each
O channel in signaling frames. In non-signaling frames, RABCD outputs the
LSB of each channel word.
O
Receive Signaling Frame. High during signaling frames; low during non-
signaling frames (and during resync)
O
Receive Signaling Select. In 193E framing, a .667kHz clock that identifies
signaling frames A and C; a 1.33kHz clock in 193S
I
Reset. A high-low transition clears all internal registers and resets counters. A
high-low-high transition initiates a resync.
I
Receive Bipolar Data Inputs. Sampled on falling of RCLK. Connect together
to receive NRZ data and disable bipolar violation monitoring circuitry.
O
Receive Carrier Loss. High if 192 consecutive 0’s appear at RPOS and
RNEG; goes low upon seeing 12.5% 1’s density.
O
Receive Bipolar Violation. High during accused bit time at RSER. If bipolar
violation detected, low otherwise.
O
Receive Frame Error. High during F-bit time when FT or FS errors occur
(193S), or when FPS or CRC errors occur (193E). Low during resync.
O
Receive Loss-of-Sync. Indicates sync status; high when internal resync is in
progress, low otherwise.
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