DS2182A View Datasheet(PDF) - Dallas Semiconductor -> Maxim Integrated

Part Name

Description

Manufacturer

DS2182A

T1 Line Monitor Chip

Dallas Semiconductor -> Maxim Integrated 

DS2182A

CHIP SELECT AND CLOCK CONTROL

All data transfers are initiated by driving the CS input low. Input data is latched on the rising edge of

SCLK and must be valid during the previous low period of SCLK to prevent momentary corruption of

register data during writes. Data is output on the falling edge of SCLK and held to the next falling edge.

All data transfers are terminated if the CS input transitions high. Port control logic is disabled and SDO is

tri-stated when CS is high.

DATA I/O

Following the eight SCLK cycles that input an address/command byte to write, a data byte is strobed into

the addressed register on the rising edge of the next eight SCLK cycles. Following an address/command

word to read, contents of the selected register are output on the falling edges of the next eight SCLK

cycles. The SDO pin is tri-stated during device write and can be connected to SDI in applications where

the host processor has a bidirectional I/O pin.

BURST MODE

The burst mode allows all on-board registers to be consecutively written to or read by the host processor.

A burst read is used to poll all registers; RSR1 and RSR2 contents are unaffected. This feature minimizes

device initialization time on system power-up or reset. Burst mode is initiated when ACB.7 is set and the

address is 0000. A burst is terminated by a low-high transition on CS .

ACB: ADDRESS COMMAND BYTE

MSB

BM

—

—

ADD3

ADD2

ADD1

ADD0

LSB

R/ W

SYMBOL

BM

—

-—

ADD3

ADD0

R/W

POSITION

ACB.7

ACB.6

ACB.5

ACB.4

ACB.1

ACB.0

FUNCTION

Burst Mode. If set (and register address is 0000), burst read or

write is enabled.

Reserved; must be 0 for operation

Reserved; must be 0 for operation

MSB of register address

LSB of register address

Read/Write Select

0 = write addressed register

1 = read addressed register

5 of 26

Share Link: