DS2182AQ View Datasheet(PDF) - Dallas Semiconductor -> Maxim Integrated

Part Name

Description

Manufacturer

DS2182AQ

T1 Line Monitor Chip

Dallas Semiconductor -> Maxim Integrated 

OOFCR: OOF COUNT REGISTER

MSB

OOF7

OOF6

OOF5

OOF4

OOF3

OOF2

OOF1

DS2182A

LSB

OOF0

SYMBOL

OOF7

OFF0

POSITION

OOFCR.7

OOFCR.0

FUNCTION

MSB of OOF event count

LSB of OOF of event count

The OOF count register (OOFCR) is an 8-bit presettable counter that records out-of-frame (OOF) events.

OOF events are defined by RCR1.5 and RCR1.6. This 8-bit counter saturates at 255 and generates an

interrupt for each occurrence after saturation if RIMR2.2 is set. The count is disabled during a loss-of-

sync condition (RLOS = 1).

FECR: FRAME ERROR COUNT REGISTER

MSB

LSB

FE7

FE6

FE5

FE4

FE3

FE2

FE1

FE0

SYMBOL

FE7

FFE0

POSITION

FECR.7

FECR.0

FUNCTION

MSB of frame error count

LSB of frame error count

The frame error count register (FECR) is an 8-bit presettable counter that records individual frame-bit

errors. In the 193E mode (RCR2.4 = 1), the FECR records bit errors in the FPS framing pattern (001011).

In the 193S mode (RCR2.4 = 0), the FECR records bit errors in both the FT (101010) and FS (001110)

framing patterns if RCR1.3 is set. If RCR1.3 is cleared, then the FECR only records bit errors in the FT

pattern. This 8-bit counter saturates at 255 and generates an interrupt for each occurrence after saturation

if RIMR2.3 is set. The count is disabled during a loss-of-sync condition (RLOS = 1).

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