DS2490 View Datasheet(PDF) - Dallas Semiconductor -> Maxim Integrated

Part Name

Description

Manufacturer

DS2490

USB to 1-WireTM Bridge Chip

Dallas Semiconductor -> Maxim Integrated 

DS2490

used. Once determined, the value code for the Pulldown Slew Rate Control parameter should be stored in

the host and always be loaded into the DS2490 after a power-on or master reset cycle.

1-WIRE TIMING DIAGRAMS

This section explains the waveforms generated by the DS2490 on the 1-Wire bus in detail. First the

communication wave forms such as the Reset/Presence Detect Sequence and the time slots are discussed.

After that follows a detailed description of the pulse function under various conditions. The wave forms

generated by the DS2490 may deviate slightly from specifications found in the “Book of DS19xx iButton

Standards” or in data sheets of 1-Wire slave devices. However, the DS2490 has been designed to ensure

that the timing requirements are met.

1-Wire Communication Wave Forms

One of the major features of the DS2490 is that it relieves the host from generating the timing of the 1-

Wire signals and sampling the 1-Wire bus at the appropriate times. The reset/presence detect sequence is

shown in Figure 5. This sequence is composed of four timing segments: the reset low time tRSTL, the

short/interrupt sampling offset tSI, the presence detect sampling offset tPDT and a delay time tFILL. The

timing segments tSI, tPDT and tFILL comprise the reset high time tRSTH where 1-Wire slave devices assert

their presence or interrupt pulse. During this time the DS2490 pulls the 1-Wire bus high with its weak

pullup current.

The values of all timing segments for all 1-Wire speed options are shown in the table. Since the

reset/presence sequence is slow compared to the time slots, the values for regular and flexible speed are

the same. Except for the falling edge of the presence pulse, all edges are controlled by the DS2490. The

shape of the uncontrolled falling edge is determined by the capacitance of the 1-Wire bus and the number,

speed and sink capability of the slave devices connected.

RESET/PRESENCE DETECT Figure 5

Speed

tRSTL tSI

Regular 512 µs 8 µs

Overdrive 64 µs

2 µs

Flexible 512 µs 8 µs

tPDT

64 µs

8 µs

64 µs

tFILL

512 µs

64 µs

512 µs

tRSTH

584 µs

74 µs

584 µs

Upon executing a 1-WIRE RESET command (see COMMUNICATION COMMANDS), the DS2490

pulls the 1-Wire bus low for tRSTL and then lets it go back to 5V. The DS2490 will now wait for the

short/interrupt sampling offset tSI to expire and then test the voltage on the 1-Wire bus to determine if

there is a short or an interrupt signal. If there is no short or interrupt (as shown in the picture), the

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