DS2490 View Datasheet(PDF) - Dallas Semiconductor -> Maxim Integrated

Part Name

Description

Manufacturer

DS2490

USB to 1-WireTM Bridge Chip

Dallas Semiconductor -> Maxim Integrated 

DS2490

DS2490 will wait for tPDT and test the voltage on the 1-Wire bus for a presence pulse. Regardless of the

result of the presence test, the DS2490 will then wait for tFILL to expire and then send the command

response byte to the host.

If the test for interrupt or short reveals a logic 0, the DS2490 will wait for 4096 µs and then test the 1-

Wire bus again. If a logic 0 is detected, the 1-Wire bus is shorted and the DS2490 feedback response for

the 1-WIRE RESET Communication Command will indicate a short detection. If a logic 1 is detected,

the device will wait for tFILL to expire, after which it will load the feedback response value for the 1-

WIRE RESET command with an Alarming Presence Pulse detect value. No additional testing for a

presence pulse will be done. The DS2490 will perform the short/interrupt testing as described also at

Overdrive speed, although interrupt signaling is only defined for regular speed.

A Write-1 and Read Data time slot is comprised of the segments tLOW1, tDSO and tHIGH. During Write-1

time slots, after the Write-1 low time tLOW1 is over, the DS2490 waits for the duration of the data sample

offset and then samples the voltage at the 1-Wire bus to read the response. After this, the waiting time

tHIGH1 must expire before the time slot is complete. A Write-0 time slot only consists of the two segments

tLOW0 and tREC0.

If the network is large or heavily loaded, flexible speed should be selected and the Write-1 low time

(tLOW1) should be extended to more than 8 µs to allow the 1-Wire bus to completely discharge. Since a

large or heavily loaded network needs more time to recharge, it is also recommended to delay sampling

the bus for reading. A higher Data Sample Offset value (tDSO) will increase the voltage margin and also

provide extra energy to the slave devices when generating a long series of Write-0 time slots. However,

the total of tLOW1 + tDSO should not exceed 22 µs. Otherwise the slave device responding may have

stopped pulling the bus low when transmitting a logic 0.

WRITE 1 AND READ DATA TIME SLOT Figure 6

Speed

tLOW1 tDSO

tHIGH1

tSLOT

Regular 8 µs

6 µs

54 µs

68 µs

Overdrive 1 µs

1 µs

8 µs

10 µs

Flexible* 8 to 15 µs 3 to 10 µs 54 µs

65 to 79 µs

*Power-up defaults for Flexible speed: tLOW1=12µs, tDSO=7µs

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