DS28E02P-TR View Datasheet(PDF) - Maxim Integrated

Part Name

Description

Manufacturer

DS28E02P-TR

1-Wire SHA-1 Authenticated 1Kb EEPROM with 1.8V Operation

Maxim Integrated 

ABRIDGED DATA SHEET

1-Wire SHA-1 Authenticated 1Kb

EEPROM with 1.8V Operation

ELECTRICAL CHARACTERISTICS (continued)

(TA = -20°C to +85°C.) (Note 1)

PARAMETER

SYMBOL

CONDITIONS

MIN TYP MAX UNITS

Programming Time

Write/Erase Cycles (Endurance)

(Notes 20, 21)

tPROG

NCY

(Note 19)

At +25°C

At +85°C

200,000

50,000

25

ms

—

Data Retention (Notes 22, 23, 24) tDR At +85°C

SHA-1 ENGINE

40

Years

Computation Current

Computation Time (Notes 5, 25)

ILCSHA (Notes 5, 18)

tCSHA

mA

Refer to full data sheet

ms

Note 1: Specifications at TA = -20°C are guaranteed by design only and not production tested.

Note 2: System requirement.

Note 3: Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times.

The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times.

Note 4: Maximum value represents the internal parasite capacitance when VPUP is first applied. If a 750Ω pullup resistor is used,

the parasite capacitance does not affect normal communications 2µs after VPUP has been applied.

Note 5: Guaranteed by design, characterization, and/or simulation only. Not production tested.

Note 6: VTL, VTH, and VHY are a function of the internal supply voltage, which is a function of VPUP, RPUP, 1-Wire timing, and

capacitive loading on IO. Lower VPUP, higher RPUP, shorter tREC, and heavier capacitive loading all lead to lower values of

VTL, VTH, and VHY.

Note 7: Voltage below which, during a falling edge on IO, a logic 0 is detected.

Note 8: The voltage on IO must be less than or equal to VILMAX at all times the master is driving IO to a logic 0 level.

Note 9: Voltage above which, during a rising edge on IO, a logic 1 is detected.

Note 10: After VTH is crossed during a rising edge on IO, the voltage on IO must drop by at least VHY to be detected as logic 0.

Note 11: The I-V characteristic is linear for voltages less than 1V.

Note 12: Applies to a single device attached to a 1-Wire line.

Note 13: Defines maximum possible bit rate. Equal to 1/(tW0LMIN + tRECMIN).

Note 14: An additional reset or communication sequence cannot begin until the reset high time has expired.

Note 15: Interval after tRSTL during which a bus master is guaranteed to sample a logic 0 on IO if there is a DS28E02 present.

Note 16: ε in Figure 12 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to VTH. The actual

maximum duration for the master to pull the line low is tW1LMAX + tF - ε and tW0LMAX + tF - ε, respectively.

Note 17: δ in Figure 12 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to the input-high

threshold of the bus master. The actual maximum duration for the master to pull the line low is tRLMAX + tF.

Note 18: Current drawn from IO during the EEPROM programming interval or SHA-1 computation.

Note 19: Refer to full data sheet for this note.

Note 20: Write-cycle endurance is degraded as TA increases.

Note 21: Not 100% production tested; guaranteed by reliability monitor sampling.

Note 22: Data retention is degraded as TA increases.

Note 23: Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to the

data sheet limit at operating temperature range is established by reliability testing.

Note 24: EEPROM writes can become nonfunctional after the data-retention time is exceeded. Long-term storage at elevated tem-

peratures is not recommended; the device can lose its write capability after 10 years at +125°C or 40 years at +85°C.

Note 25: Refer to full data sheet for this note.

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