DS8005 View Datasheet(PDF) - Maxim Integrated

Part Name

Description

Manufacturer

DS8005

Smart Card Interface

Maxim Integrated 

DS8005

Smart Card Interface

The following procedure summarizes the procedure when

switching from card A to card B, and vice versa:

Note: The host must have previously recorded the state

of the control pins for the card B interface.

1) The host must record the state of the control pins for

the card A interface.

2) Ensure that the control pin configuration does not

change state less than 220µs before changing the

SEL_AB pin.

3) Switch SEL_AB to the desired valued.

4) Within 78µs, the host must restore the control pins

the state previously recorded for the card B interface.

5) Wait at least 42µs before reconfiguring the control

pins to change card B to a new state.

Note that the behavior of the OFF and OFF2 pins is depen-

dent on the SEL_AB pin. OFF always refers to the active

interface, and OFF2 always reports events on the inactive

interface. This allows the device to monitor for card inser-

tion and removal on both interfaces simultaneously. See

Figure 10 for details on the behavior of the SEL_AB, OFF,

and OFF2 pins with regard to card presence.

Applications Information

Performance can be affected by the layout of the applica-

tion. For example, an additional cross-capacitance of 1pF

between card reader contacts C2 (RST_) and C3 (CLK_)

or C2 (RST_) and C7 (I/O_) can cause contact C2 to be

polluted with high-frequency noise from C3 (or C7). In

this case, include a 100pF capacitor between contacts

C2 and CGND.

Application recommendations include the following:

• Ensure there is ample ground area around the device

and the connector; place the device very near to the

connector; decouple the VDD and VDDA lines sepa-

rately. These lines are best positioned under the con-

nector.

• The device and the host microcontroller must use the

same VDD supply. Pins CLKDIV1, CLKDIV2, RSTIN,

PRES_, I/OIN, 5V/3V, 1_8V, CMDVCC, and OFF are

referenced to VDD; if pin XTAL1 is to be driven by an

external clock, also reference this pin to VDD.

• Trace C3 (CLK) should be placed as far as possible

from the other traces.

• The trace connecting CGND to C5 (GND) should be

straight (the two capacitors on C1 (VCC_) should be

connected to this ground trace).

• Avoid ground loops between CGND and GND.

• Decouple VDDA and VDD separately. If two supplies

are the same in the application, they should be con-

nected in a star on the main trace

With all these layout precautions, noise should be kept to

an acceptable level and jitter on C3 (CLK_) should be less

than 100ps. Reference layouts are available on request.

Technical Support

For technical support, go to https://support.maximinte-

grated.com/micro.

www.maximintegrated.com

Maxim Integrated │  18

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