DSP56KFAMUM/AD(1996) View Datasheet(PDF) - Motorola => Freescale

Part Name

Description

Manufacturer

DSP56KFAMUM/AD
(Rev.:1996)

24-BIT DIGITAL SIGNAL PROCESSOR

Motorola => Freescale 

Specifications

Internal Clocks

INTERNAL CLOCKS

For each occurrence of TH, TL, TC or ICYC, substitute with the numbers in Table 2-4.

DF and MF are PLL division and multiplication factors set in registers.

Table 2-4 Internal Clocks

Characteristics

Symbol

Expression

Internal Operation Frequency

Internal Clock High Period

• With PLL disabled

• With PLL enabled and MF ≤ 4

• With PLL enabled and MF > 4

Internal Clock Low Period

• With PLL disabled

• With PLL enabled and MF ≤ 4

• With PLL enabled and MF > 4

Internal Clock Cycle Time

Instruction Cycle Time

f

TH

TL

TC

ICYC

ETH

(Min) 0.48 × TC

(Max) 0.52 × TC

(Min) 0.467 × TC

(Max) 0.533 × TC

ETL

(Min) 0.48 × TC

(Max) 0.52 × TC

(Min) 0.467 × TC

(Max) 0.533 × TC

ETC × DF/MF

2 × TC

MOTOROLA

DSP56002/D, Rev. 3

2-5

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