DSP56KFAMUM/AD(1996) View Datasheet(PDF) - Motorola => Freescale

Part Name

Description

Manufacturer

DSP56KFAMUM/AD
(Rev.:1996)

24-BIT DIGITAL SIGNAL PROCESSOR

Motorola => Freescale 

FEATURES

DSP56002

Features

Digital Signal Processing Core

• Efficient 24-bit DSP56000 core

• Up to 40 Million Instructions Per Second (MIPS), 25 ns instruction cycle at

80 MHz; up to 33 MIPS, 30.3 ns instruction cycle at 66 MHz

• Up to 240 Million Operations Per Second (MOPS) at 80 MHz; up to 198 MOPS

at 66 MHz

• Performs a 1024-point complex Fast Fourier Transform (FFT) in 59,898 clocks

• Highly parallel instruction set with unique DSP addressing modes

• Two 56-bit accumulators including extension bits

• Parallel 24 × 24-bit multiply-accumulate in 1 instruction cycle (2 clock cycles)

• Double precision 48 × 48-bit multiply with 96-bit result in 6 instruction cycles

• 56-bit addition/subtraction in 1 instruction cycle

• Fractional and integer arithmetic with support for multiprecision arithmetic

• Hardware support for block-floating point FFT

• Hardware nested DO loops

• Zero-overhead fast interrupts (2 instruction cycles)

• Four 24-bit internal data buses and three 16-bit internal address buses for

maximum information transfer on-chip

Memory

• On-chip Harvard architecture permitting simultaneous accesses to program

and two data memories

• 512 × 24-bit on-chip Program RAM and 64 × 24-bit bootstrap ROM

• Two 256 × 24-bit on-chip data RAMs

• Two 256 × 24-bit on-chip data ROMs containing sine, A-law, and µ-law tables

• External memory expansion with 16-bit address and 24-bit data buses

• Bootstrap loading from external data bus, Host Interface, or Serial

Communications Interface

MOTOROLA

DSP56002/D, Rev. 3

iii

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