DSP56011 View Datasheet(PDF) - Motorola => Freescale

Part Name

Description

Manufacturer

DSP56011

24-BIT DVD DIGITAL SIGNAL PROCESSOR

Motorola => Freescale 

Design Considerations

Host Port Considerations

HOST PORT CONSIDERATIONS

Careful synchronization is required when reading multi-bit registers that are written

by another asynchronous system. This is a common problem when two

P R E L I M I N A R Y asynchronous systems are connected. The situation exists in the Host Interface. The

following paragraphs present considerations for proper operation.

Host Programming Considerations

• Unsynchronized Reading of Receive Byte Registers—When reading receive

byte registers, RXH or RXL, the host program should use interrupts or poll the

RXDF flag which indicates that data is available. This assures that the data in

the receive byte registers will be stable.

• Overwriting Transmit Byte Registers—The host program should not write to

the transmit byte registers, TXH or TXL, unless the TXDE bit is set, indicating

that the transmit byte registers are empty. This guarantees that the transmit

byte registers will transfer valid data to the HRX register.

• Synchronization of Status Bits from DSP to Host—HC, HOREQ, DMA, HF3,

HF2, TRDY, TXDE, and RXDF status bits are set or cleared from inside the

DSP and read by the host processor (refer to the User’s Manual for descriptions

of these status bits). The host can read these status bits very quickly without

regard to the clock rate used by the DSP, but the state of the bit could be

changing during the read operation. Generally, this is not a system problem,

since the bit will be read correctly in the next pass of any host polling routine.

However, if the host asserts HEN for more than timing number 31, with

a minimum cycle time of timing number 31 + 32, then these status bits are

guaranteed to be stable. Exercise care when reading status bits HF3 and HF2

as an encoded pair. If the DSP changes HF3 and HF2 from 00 to 11, there is a

small probability that the host could read the bits during the transition and

receive 01 or 10 instead of 11. If the combination of HF3 and HF2 has

significance, the host could read the wrong combination. Therefore, read the

bits twice and check for consensus.

• Overwriting the Host Vector—The host program should change the Host

Vector register only when the Host Command bit (HC) is clear. This change

will guarantee that the DSP interrupt control logic will receive a stable vector.

• Cancelling a Pending Host Command Exception—The host processor may

elect to clear the HC bit to cancel the host command exception request at any

time before it is recognized by the DSP. Because the host does not know

exactly when the exception will be recognized (due to exception processing

synchronization and pipeline delays), the DSP may execute the host

Preliminary Information

MOTOROLA

DSP56011 Technical Data Sheet, Rev. 1

4-7

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