DSP56309/D View Datasheet(PDF) - Motorola => Freescale

Part Name

Description

Manufacturer

DSP56309/D

24-Bit Digital Signal Processor

Motorola => Freescale 

Freescale Semiconductor, Inc.

Power Consumption Benchmark

;------------------------------------------------------------------------

;

;

EQUATES for Serial Communications Interface (SCI)

;

;------------------------------------------------------------------------

;

Register Addresses

M_STXH EQU $FFFF97

M_STXM EQU $FFFF96

M_STXL EQU $FFFF95

M_SRXH EQU $FFFF9A

M_SRXM EQU $FFFF99

M_SRXL EQU $FFFF98

M_STXA EQU $FFFF94

M_SCR EQU $FFFF9C

M_SSR EQU $FFFF93

M_SCCR EQU $FFFF9B

; SCI Transmit Data Register (high)

; SCI Transmit Data Register (middle)

; SCI Transmit Data Register (low)

; SCI Receive Data Register (high)

; SCI Receive Data Register (middle)

; SCI Receive Data Register (low)

; SCI Transmit Address Register

; SCI Control Register

; SCI Status Register

; SCI Clock Control Register

;

SCI Control Register Bit Flags

M_WDS EQU $7

M_WDS0 EQU 0

M_WDS1 EQU 1

M_WDS2 EQU 2

M_SSFTD EQU 3

M_SBK EQU 4

M_WAKE EQU 5

M_RWU EQU 6

M_WOMS EQU 7

M_SCRE EQU 8

M_SCTE EQU 9

M_ILIE EQU 10

M_SCRIE EQU 11

M_SCTIE EQU 12

M_TMIE EQU 13

M_TIR EQU 14

M_SCKP EQU 15

M_REIE EQU 16

; Word Select Mask (WDS0-WDS3)

; Word Select 0

; Word Select 1

; Word Select 2

; SCI Shift Direction

; Send Break

; Wakeup Mode Select

; Receiver Wakeup Enable

; Wired-OR Mode Select

; SCI Receiver Enable

; SCI Transmitter Enable

; Idle Line Interrupt Enable

; SCI Receive Interrupt Enable

; SCI Transmit Interrupt Enable

; Timer Interrupt Enable

; Timer Interrupt Rate

; SCI Clock Polarity

; SCI Error Interrupt Enable (REIE)

;

SCI Status Register Bit Flags

M_TRNE EQU 0

M_TDRE EQU 1

M_RDRF EQU 2

M_IDLE EQU 3

M_OR EQU 4

M_PE EQU 5

M_FE EQU 6

M_R8 EQU 7

; Transmitter Empty

; Transmit Data Register Empty

; Receive Data Register Full

; Idle Line Flag

; Overrun Error Flag

; Parity Error

; Framing Error Flag

; Received Bit 8 (R8) Address

;

SCI Clock Control Register

M_CD EQU $FFF

M_COD EQU 12

M_SCP EQU 13

M_RCM EQU 14

M_TCM EQU 15

; Clock Divider Mask (CD0-CD11)

; Clock Out Divider

; Clock Prescaler

; Receive Clock Mode Source Bit

; Transmit Clock Source Bit

;------------------------------------------------------------------------

;

;

EQUATES for Synchronous Serial Interface (SSI)

;

;------------------------------------------------------------------------

;

;

Register Addresses Of SSI0

M_TX00 EQU $FFFFBC

; SSI0 Transmit Data Register 0

M_TX01 EQU $FFFFBB

; SSIO Transmit Data Register 1

M_TX02 EQU $FFFFBA

; SSIO Transmit Data Register 2

M_TSR0 EQU $FFFFB9

; SSI0 Time Slot Register

M_RX0 EQU $FFFFB8

; SSI0 Receive Data Register

M_SSISR0 EQU $FFFFB7 ; SSI0 Status Register

M_CRB0 EQU $FFFFB6

; SSI0 Control Register B

M_CRA0 EQU $FFFFB5

; SSI0 Control Register A

M_TSMA0 EQU $FFFFB4

; SSI0 Transmit Slot Mask Register A

M_TSMB0 EQU $FFFFB3

; SSI0 Transmit Slot Mask Register B

M_RSMA0 EQU $FFFFB2

; SSI0 Receive Slot Mask Register A

M_RSMB0 EQU $FFFFB1

; SSI0 Receive Slot Mask Register B

A-5

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