DSP56309/D View Datasheet(PDF) - Motorola => Freescale
Part Name
Description
Manufacturer
DSP56309/D Datasheet PDF : 112 Pages
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Freescale Semiconductor, Inc.
AC Electrical Characteristics
Table 2-5. Clock Operation
No.
Characteristics
1 Frequency of EXTAL (EXTAL Pin Frequency)
The rise and fall time of this external clock should be 3 ns maximum.
2 EXTAL input high1, 2
• With PLL disabled (46.7%–53.3% duty cycle6)
• With PLL enabled (42.5%–57.5% duty cycle6)
3 EXTAL input low1, 2
• With PLL disabled (46.7%–53.3% duty cycle6)
• With PLL enabled (42.5%–57.5% duty cycle6)
4 EXTAL cycle time2
• With PLL disabled
• With PLL enabled
5 Internal clock change from EXTAL fall with PLL disabled
6 a.Internal clock rising edge from EXTAL rising edge with PLL enabled
(MF = 1 or 2 or 4, PDF = 1, Ef > 15 MHz)3,5
Symbol
Ef
100 MHz
Min
Max
0
100.0
ETH
4.67 ns
∞
4.25 ns 157.0 µs
ETL
4.67 ns
∞
4.25 ns 157.0 µs
ETC
10.00 ns
∞
10.00 ns 273.1 µs
4.3 ns
11.0 ns
0.0 ns
1.8 ns
b. Internal clock falling edge from EXTAL falling edge with PLL enabled
(MF ≤ 4, PDF ≠ 1, Ef / PDF > 15 MHz)3,5
7 Instruction cycle time = ICYC = TC4
(see Figure 2-4) (46.7%–53.3% duty cycle)
ICYC
• With PLL disabled
• With PLL enabled
0.0 ns
1.8 ns
20.0 ns
10.00 ns
∞
8.53 µs
Notes: 1. Measured at 50 percent of the input transition.
2. The maximum value for PLL enabled is given for minimum VCO frequency (see Table 2-4) and
maximum MF.
3. Periodically sampled and not 100 percent tested.
4. The maximum value for PLL enabled is given for minimum VCO frequency and maximum DF.
5. The skew is not guaranteed for any other MF value.
6. The indicated duty cycle is for the specified maximum frequency for which a part is rated. The minimum
clock high or low time required for correction operation, however, remains the same at lower operating
frequencies; therefore, when a lower clock frequency is used, the signal symmetry may vary from the
specified duty cycle as long as the minimum high time and low time requirements are met.
2.6.3 Phase Lock Loop (PLL) Characteristics
Table 2-6. PLL Characteristics
Characteristics
100 MHz
Unit
Min
Max
Voltage Controlled Oscillator (VCO) frequency when PLL enabled
(MF × Ef × 2/PDF)
PLL external capacitor (PCAP pin to VCCP) (CPCAP1)
• @ MF ≤ 4
• @ MF > 4
30
200
MHz
(580 × MF) − 100 (780 × MF) − 140 pF
830 × MF
1470 × MF
pF
Note:
CPCAP is the value of the PLL capacitor (connected between the PCAP pin and VCCP) computed using the
appropriate expression listed above.
2-6
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