DSP56309/D View Datasheet(PDF) - Motorola => Freescale
Part Name
Description
Manufacturer
DSP56309/D Datasheet PDF : 112 Pages
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Freescale Semiconductor, Inc.
DSP56309 Features
High-Performance DSP56300 Core
• 100 million instructions per second (MIPS) with a 100 MHz clock at 3.3 V nominal
• Data Arithmetic Logic Unit (Data ALU) with fully pipelined 24 × 24-bit parallel
Multiplier-Accumulator (MAC), 56-bit parallel barrel shifter (fast shift and normalization; bit stream
generation and parsing), conditional ALU instructions, and 24-bit or 16-bit arithmetic support under
software control
• Program Control Unit (PCU) with Position Independent Code (PIC) support, addressing modes
optimized for DSP applications (including immediate offsets), internal instruction cache controller,
internal memory-expandable hardware stack, nested hardware DO loops, and fast auto-return interrupts
• Direct Memory Access (DMA) with six DMA channels supporting internal and external accesses;
one-, two-, and three-dimensional transfers (including circular buffering); end-of-block-transfer
interrupts; and triggering from interrupt lines and all peripherals
• Phase Lock Loop (PLL) allows change of low-power Divide Factor (DF) without loss of lock and
output clock with skew elimination
• Hardware debugging support including On-Chip Emulation (OnCE™) module, Joint Test Action
Group (JTAG) Test Access Port (TAP)
Internal Peripherals
• Enhanced 8-bit parallel host interface (HI08) supports a variety of buses (for example, ISA) and
provides glueless connection to a number of industry-standard microcomputers, microprocessors, and
DSPs
• Two enhanced synchronous serial interfaces (ESSI), each with one receiver and three transmitters
(allows six-channel home theater)
• Serial communications interface (SCI) with baud rate generator
• Triple timer module
• Up to thirty-four programmable general-purpose input/output (GPIO) pins, depending on which
peripherals are enabled
Internal Memory
• 192 × 24-bit bootstrap ROM
• 34 K × 24-bit RAM total
• Program RAM, Instruction Cache, X data RAM, and Y data RAM sizes are programmable:
Program RAM
Size
20480 × 24 bits
19456 × 24 bits
24576 × 24 bits
23552 × 24 bits
Instruction
Cache Size
0
1024 × 24-bit
0
1024 × 24-bit
X Data RAM
Size
7168 × 24 bits
7168 × 24 bits
5120 × 24 bits
5120 × 24 bits
Y Data RAM
Size
7168 × 24 bits
7168 × 24 bits
5120 × 24 bits
5120 × 24 bits
Instruction
Cache
disabled
enabled
disabled
enabled
Switch Mode
disabled
disabled
enabled
enabled
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For More Information On This Product,
Go to: www.freescale.com
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