DSP56311VF150 View Datasheet(PDF) - Motorola => Freescale

Part Name

Description

Manufacturer

DSP56311VF150

24-Bit Digital Signal Processor

Motorola => Freescale 

External Memory Expansion Port (Port A)

Table 1-8. External Bus Control Signals (Continued)

Signal

Name

Type

State During

Reset, Stop, or

Wait

Signal Description

BR

Output Reset: Output

Bus Request—Asserted when the DSP requests bus mastership. BR is

(deasserted)

deasserted when the DSP no longer needs the bus. BR may be

asserted or deasserted independently of whether the DSP56311 is a

State during

bus master or a bus slave. Bus “parking” allows BR to be deasserted

Stop/Wait depends even though the DSP56311 is the bus master. (See the description of

on BRH bit setting: bus “parking” in the BB signal description.) The bus request hold (BRH)

• BRH = 0: Output, bit in the BCR allows BR to be asserted under software control even

deasserted

though the DSP does not need the bus. BR is typically sent to an

• BRH = 1: Maintains external bus arbitrator that controls the priority, parking, and tenure of

last state (that is, if each master on the same external bus. BR is affected only by DSP

asserted, remains requests for the external bus, never for the internal bus. During

asserted)

hardware reset, BR is deasserted and the arbitration is reset to the bus

slave state.

BG

Input Ignored Input

Bus Grant—Asserted by an external bus arbitration circuit when the

DSP56311 becomes the next bus master. When BG is asserted, the

DSP56311 must wait until BB is deasserted before taking bus

mastership. When BG is deasserted, bus mastership is typically given

up at the end of the current bus cycle. This may occur in the middle of an

instruction that requires more than one external bus cycle for execution.

BB

Input/ Ignored Input

Output

The default operation of this bit requires a set-up and hold time as

specified in Chapter 2. An alternate mode can be invoked: set the

asynchronous bus arbitration enable (ABE) bit (Bit 13) in the Operating

Mode Register. When this bit is set, BG and BB are synchronized

internally. This eliminates the respective set-up and hold time

requirements but adds a required delay between the deassertion of an

initial BG input and the assertion of a subsequent BG input.

Bus Busy—Indicates that the bus is active. Only after BB is deasserted

can the pending bus master become the bus master (and then assert

the signal again). The bus master may keep BB asserted after ceasing

bus activity regardless of whether BR is asserted or deasserted. Called

“bus parking,” this allows the current bus master to reuse the bus

without rearbitration until another device requires the bus. BB is

deasserted by an “active pull-up” method (that is, BB is driven high and

then released and held high by an external pull-up resistor).

The default operation of this signal requires a set-up and hold time as

specified in Chapter 2. An alternative mode can be invoked by setting

the ABE bit (Bit 13) in the Operating Mode Register. When this bit is set,

BG and BB are synchronized internally. See BG for additional

information.

CAS

Output Tri-stated

Note: BB requires an external pull-up resistor.

Column Address Strobe—When the DSP is the bus master, CAS is an

active-low output used by DRAM to strobe the column address.

Otherwise, if the Bus Mastership Enable (BME) bit in the DRAM control

register is cleared, the signal is tri-stated.

Note: DRAM access is not supported above 100 MHz.

1-7

Share Link: