DSP56311UM View Datasheet(PDF) - Motorola => Freescale

Part Name

Description

Manufacturer

DSP56311UM

24-Bit Digital Signal Processor

Motorola => Freescale 

External Memory Expansion Port (Port A)

Table 1-8. External Bus Control Signals (Continued)

Signal

Name

Type

State During

Reset, Stop, or

Wait

Signal Description

BCLK

Output Tri-stated

Bus Clock

When the DSP is the bus master, BCLK is active when the ATE bit in the

Operating Mode Register is set. When BCLK is active and synchronized

to CLKOUT by the internal PLL, BCLK precedes CLKOUT by one-fourth

of a clock cycle.

BCLK

Output Tri-stated

Note: At operating frequencies above 100 MHz, this signal produces a

low-amplitude waveform that is not usable externally by other devices.

Bus Clock Not

When the DSP is the bus master, BCLK is the inverse of the BCLK

signal. Otherwise, the signal is tri-stated.

Note: At operating frequencies above 100 MHz, this signal produces a

low-amplitude waveform that is not usable externally by other devices.

1-8

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