DSP56311/D View Datasheet(PDF) - Motorola => Freescale
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Description
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DSP56311/D Datasheet PDF : 100 Pages
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Interrupt and Mode Control
1.7 Interrupt and Mode Control
The interrupt and mode control signals select the chip operating mode as it comes out of hardware reset.
After RESET is deasserted, these inputs are hardware interrupt request lines.
Table 1-9. Interrupt and Mode Control
Signal Name
MODA
IRQA
MODB
IRQB
MODC
IRQC
MODD
IRQD
RESET
Type
Input
State During
Reset
Schmitt-trigger
Input
Signal Description
Mode Select A—MODA, MODB, MODC, and MODD select one
of 16 initial chip operating modes, latched into the Operating
Mode Register when the RESET signal is deasserted.
Input
Input
Schmitt-trigger
Input
External Interrupt Request A—After reset, this input becomes a
level-sensitive or negative-edge-triggered, maskable interrupt
request input during normal instruction processing. If the
processor is in the STOP or WAIT standby state and IRQA is
asserted, the processor exits the STOP or WAIT state.
Mode Select B—MODA, MODB, MODC, and MODD select one
of 16 initial chip operating modes, latched into the Operating
Mode Register when the RESET signal is deasserted.
Input
Input
Schmitt-trigger
Input
External Interrupt Request B—After reset, this input becomes a
level-sensitive or negative-edge-triggered, maskable interrupt
request input during normal instruction processing. If the
processor is in the WAIT standby state and IRQB is asserted, the
processor exits the WAIT state.
Mode Select C—MODA, MODB, MODC, and MODD select one
of 16 initial chip operating modes, latched into the Operating
Mode Register when the RESET signal is deasserted.
Input
Input
Schmitt-trigger
Input
External Interrupt Request C—After reset, this input becomes a
level-sensitive or negative-edge-triggered, maskable interrupt
request input during normal instruction processing. If the
processor is in the WAIT standby state and IRQC is asserted, the
processor exits the WAIT state.
Mode Select D—MODA, MODB, MODC, and MODD select one
of 16 initial chip operating modes, latched into the Operating
Mode Register when the RESET signal is deasserted.
Input
Input
Schmitt-trigger
Input
External Interrupt Request D—After reset, this input becomes a
level-sensitive or negative-edge-triggered, maskable interrupt
request input during normal instruction processing. If the
processor is in the WAIT standby state and IRQD is asserted, the
processor exits the WAIT state.
Reset—Places the chip in the Reset state and resets the internal
phase generator. The Schmitt-trigger input allows a slowly rising
input (such as a capacitor charging) to reset the chip reliably.
When the RESET signal is deasserted, the initial chip operating
mode is latched from the MODA, MODB, MODC, and MODD
inputs. The RESET signal must be asserted after powerup.
1-9
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