DSP56311 View Datasheet(PDF) - Motorola => Freescale

Part Name

Description

Manufacturer

DSP56311

24-Bit Digital Signal Processor

Motorola => Freescale 

Technical Data

DSP56311/D

Rev. 4, 10/2002

24-Bit Digital Signal

Processor

The DSP56311 is

intended for

applications requiring

a large amount of

on-chip memory, such

as networking and

wireless infrastructure

applications. The

EFCOP can accelerate

general filtering

applications, such as

echo-cancellation

applications,

correlation, and

general-purpose

convolution-based

algorithms.

3

16

66

Memory Expansion Area

SCI

Triple

Timer

Address

Generation

Unit

Six Channel

DMA Unit

Bootstrap

ROM

Internal

Data

Bus

Switch

HI08

ESSI

EFCOP

Peripheral

Expansion Area

Program

RAM

32 K × 24 bits

or

31 K × 24 bits

and

Instruction

Cache

1024 × 24 bits

X Data

RAM

48 K × 24 bits

Y Data

RAM

48 K × 24 bits

YAB

XAB

PAB

DAB

24-Bit

DSP56300

Core

DDB

YDB

XDB

PDB

GDB

External

Address

Bus

Switch

18

Address

External

Bus

Interface

and

I - Cache

Control

13

Control

External

Data

Bus

Switch

24

Data

Clock

Generator

PLL

Program

Interrupt

Controller

EXTAL

XTAL

RESET

PINIT/NMI

PCAP

Program

Decode

Controller

MODA/IRQA

MODB/IRQB

MODC/IRQC

MODD/IRQD

Power

Management

Program

Address

Generator

Data ALU

24 × 24 + 56 → 56-bit MAC

Two 56-bit Accumulators

56-bit Barrel Shifter

JTAG

OnCE™

5

DE

Figure 1. DSP56311 Block Diagram

The Motorola DSP56311, a member of the

DSP56300 Digital Signal Processor (DSP) family,

supports network applications with general

filtering operations. The Enhanced Filter

Coprocessor (EFCOP) executes filter algorithms in

parallel with core operations enhancing signal

quality with no impact on channel throughput or

total channels supported. The result is increased

overall performance. Like the other DSP56300

family members, the DSP56311 uses a

high-performance, single-clock-cycle-per-

instruction engine (DSP56000 code-compatible), a

barrel shifter, 24-bit addressing, an instruction

cache, and a direct memory access (DMA)

controller (see Figure 1). The DSP56311 performs

at 150 million instructions per second (MIPS),

attaining 270 MIPS when the EFCOP is in use. It

operates with an internal 150 MHz clock with a

1.8 volt core and independent 3.3 volt input/output

(I/O) power.

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