AC Electrical Characteristics
2.5.2
External Clock Operation
The DSP56311 system clock is derived from the on-chip oscillator or is externally supplied. To use the
on-chip oscillator, connect a crystal and associated resistor/capacitor components to EXTAL and XTAL;
examples are shown in Figure 2-1.
EXTAL
XTAL
R1
R2
EXTAL
XTAL
R
C
C
XTAL1
Fundamental Frequency
Fork Crystal Oscillator
Note: Ensure that in
the PCTL Register:
s XTLD (bit 16) = 0
s If fOSC ≤ 200 kHz,
XTLR (bit 15) = 1
C
XTAL1
C
Fundamental Frequency
Crystal Oscillator
Note: Make sure that
in the PCTL Register:
s XTLD (bit 16) = 0
s If fOSC > 200 kHz,
XTLR (bit 15) = 0
Suggested Component Values:
fOSC = 32.768 kHz
R1 = 3.9 MΩ ± 10%
C = 22 pF ± 20%
R2 = 200 kΩ ± 10%
Calculations are for a 32.768 kHz crystal with the
following parameters:
s load capacitance (CL) of 12.5 pF,
s shunt capacitance (C0) of 1.8 pF,
s series resistance of 40 kΩ, and
s drive level of 1 µW.
Suggested Component Values:
fOSC = 4 MHz
R = 680 kΩ ± 10%
fOSC = 20 MHz
R = 680 kΩ ± 10%
C = 56 pF ± 20%
C = 22 pF ± 20%
Calculations are for a 4/20 MHz crystal with the
following parameters:
s CLof 30/20 pF,
s C0 of 7/6 pF,
s series resistance of 100/20 Ω, and
s drive level of 2 mW.
Figure 2-1. Crystal Oscillator Circuits
If an externally-supplied square wave voltage source is used, disable the internal oscillator circuit during
bootup by setting XTLD (PCTL Register bit 16 = 1—see the DSP56311 User’s Manual). The external
square wave source connects to EXTAL; XTAL is not physically connected to the board or socket. Figure
2-2 shows the relationship between the EXTAL input and the internal clock and CLKOUT.
EXTAL
VILX ETH
2
5
CLKOUT with PLL
disabled
ETL
3
4
ETC
CLKOUT with PLL
enabled
Midpoint
VIHX
Note: The midpoint is 0.5 (VIHX + VILX).
5
7
6a
6b
7
Figure 2-2. External Clock Timing
2-5