DSP56311VF150 View Datasheet(PDF) - Motorola => Freescale

Part Name

Description

Manufacturer

DSP56311VF150

24-Bit Digital Signal Processor

Motorola => Freescale 

DSP56311 Features

High-Performance DSP56300 Core

• 150 million instructions per second (MIPS) (270 MIPS using the EFCOP in filtering applications) with

a 150 MHz clock at 1.8 V core and 3.3 V I/O

• Object code compatible with the DSP56000 core with highly parallel instruction set

• Data Arithmetic Logic Unit (Data ALU) with fully pipelined 24 × 24-bit parallel

Multiplier-Accumulator (MAC), 56-bit parallel barrel shifter (fast shift and normalization; bit stream

generation and parsing), conditional ALU instructions, and 24-bit or 16-bit arithmetic support under

software control

• Program Control Unit (PCU) with Position Independent Code (PIC) support, addressing modes

optimized for DSP applications (including immediate offsets), on-chip instruction cache controller,

on-chip memory-expandable hardware stack, nested hardware DO loops, and fast auto-return interrupts

• Direct Memory Access (DMA) with six DMA channels supporting internal and external accesses;

one-, two-, and three-dimensional transfers (including circular buffering); end-of-block-transfer

interrupts; and triggering from interrupt lines and all peripherals

• Phase Lock Loop (PLL) allows change of low-power Divide Factor (DF) without loss of lock and

output clock with skew elimination

• Hardware debugging support including On-Chip Emulation (OnCE™) module, Joint Test Action

Group (JTAG) Test Access Port (TAP)

Enhanced Filtering Coprocessor (EFCOP)

• On-chip 24 × 24-bit filtering and echo-cancellation coprocessor that runs in parallel to the DSP core

• Operation at the same frequency as the core (up to 150 MHz)

• Support for a variety of filter modes, some of which are optimized for cellular base station applications:

— Real Finite Impulse Response (FIR) with real taps

— Complex FIR with complex taps

— Complex FIR generating pure real or pure imaginary outputs alternately

— A 4-bit decimation factor in FIR filters, thus providing a decimation ratio up to 16

— Direct form 1 (DFI) Infinite Impulse Response (IIR) filter

— Direct form 2 (DFII) IIR filter

— Four scaling factors (1, 4, 8, 16) for IIR output

— Adaptive FIR filter with true least mean square (LMS) coefficient updates

— Adaptive FIR filter with delayed LMS coefficient updates

On-Chip Peripherals

• Enhanced DSP56000-like 8-bit parallel host interface (HI08) supports a variety of buses (for example,

ISA) and provides glueless connection to a number of industry-standard microcomputers,

microprocessors, and DSPs

• Two enhanced synchronous serial interfaces (ESSI), each with one receiver and three transmitters

(allows six-channel home theater)

• Serial communications interface (SCI) with baud rate generator

• Triple timer module

• Up to 34 programmable general-purpose input/output (GPIO) pins, depending on which peripherals are

enabled

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