DSP56311 View Datasheet(PDF) - Motorola => Freescale
Part Name
Description
Manufacturer
DSP56311 Datasheet PDF : 100 Pages
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On-Chip Memories
• 192 × 24-bit bootstrap ROM
• 128 K RAM total
• Program RAM, Instruction Cache, X data RAM, and Y data RAM sizes are programmable:
Program
RAM Size
Instruction
Cache Size
X Data RAM Size* Y Data RAM Size*
Instruction
Cache
32 K × 24-bit
0
48 K × 24-bit
48 K × 24-bit
disabled
31 K × 24-bit
1024 × 24-bit
48 K × 24-bit
48 K × 24-bit
enabled
96 K × 24-bit
0
16 K × 24-bit
16 K × 24-bit
disabled
95 K × 24-bit
1024 × 24-bit
16 K × 24-bit
16 K × 24-bit
enabled
80 K × 24-bit
0
24 K × 24-bit
24 K × 24-bit
disabled
79 K × 24-bit
1024 × 24-bit
24 K × 24-bit
24 K × 24-bit
enabled
64 K × 24-bit
0
32 K × 24-bit
32 K × 24-bit
disabled
63 K × 24-bit
1024 × 24-bit
32 K × 24-bit
32 K × 24-bit
enabled
48 K × 24-bit
0
40 K × 24-bit
40 K × 24-bit
disabled
47 K × 24-bit
1024 × 24-bit
40 K × 24-bit
40 K × 24-bit
enabled
*Includes 10 K × 24-bit shared memory (that is, memory shared by the core and the EFCOP)
Switch
Mode
disabled
disabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
MSW1 MSW0
0/1
0/1
0/1
0/1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
Off-Chip Memory Expansion
• Data memory expansion to two 256 K × 24-bit word memory spaces using the standard external
address lines
• Program memory expansion to one 256 K × 24-bit words memory space using the standard external
address lines
• External memory expansion port
• Chip Select Logic for glueless interface to static random access memory (SRAMs)
• On-chip DRAM Controller for glueless interface to dynamic random access memory (DRAMs) up to
100 MHz operating frequency
Reduced Power Dissipation
• Very low-power CMOS design
• Wait and Stop low-power standby modes
• Fully static design specified to operate down to 0 Hz (dc)
• Optimized power management circuitry (instruction-dependent, peripheral-dependent, and
mode-dependent)
Packaging
The DSP56311 is available in a 196-pin MAP-BGA package.
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