DSP56311VF150 View Datasheet(PDF) - Motorola => Freescale
Part Name
Description
Manufacturer
DSP56311VF150 Datasheet PDF : 100 Pages
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Index
Index-2
Host Port Control Register (HPCR) 1-10, 1-12
Host Request
Double 1-2
Single 1-2
Host Request (HR) 1-2
I
information sources v
instruction cache iii
internal clocks 2-4
interrupt and mode control 1-1, 1-8
interrupt control 1-8
interrupt timing 2-7
external level-sensitive fast 2-9
external negative edge-triggered 2-10
interrupts
EFCOP A-12
J
Joint Test Action Group (JTAG)
interface 1-18
JTAG iii
JTAG Port
reset timing diagram 2-39
timing 2-39
JTAG/OnCE Interface signals
Debug Event signal (DE signal) 1-18
JTAG/OnCE port 1-1, 1-2
K
keeper circuit
design considerations 4-3
M
MAP-BGA
ball grid drawing (bottom) 3-3
ball grid drawing (top) 3-2
mechanical drawing 3-10
maximum ratings 2-1, 2-2
memory expansion port iii
mode control 1-8
Mode select timing 2-7
multiplexed bus 1-2
multiplexed bus timings
read 2-28
write 2-29
N
non-multiplexed bus 1-2
non-multiplexed bus timings
read 2-26
write 2-27
O
off-chip memory iii
OnCE module iii
Debug request 2-40
on-chip DRAM controller iv
On-Chip Emulation (OnCE) module
interface 1-18
On-Chip Emulation module iii
on-chip memory iii
operating mode select timing 2-10
ordering information Back Cover
P
package
MAP-BGA description 3-2, 3-3, 3-10
Phase-Lock Loop (PLL) 1-1, 2-6
design considerations 4-5
performance issues 4-5
PLL 1-4
Port A 1-1, 1-5, 2-11
Port B 1-1, 1-2, 1-11
Port C 1-1, 1-2, 1-13
Port D 1-1, 1-2, 1-14
Port E 1-1
power 1-1, 1-2, 1-3
power consumption
design considerations 4-4
power consumption benchmark test A-1
power management iv
program memory expansion iv
program RAM iii
R
recovery from Stop state using IRQA 2-10
reset
clock signals 1-4
interrupt signals 1-8
JTAG signals 1-18
mode control 1-8
OnCE signals 1-18
PLL signals 1-4
Reset timing 2-7, 2-9
ROM, bootstrap iii
S
Serial Communication Interface (SCI) iii, 1-1,
1-2, 1-16
Asynchronous mode timing 2-31
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