DSP56364UM View Datasheet(PDF) - Motorola => Freescale

Part Name

Description

Manufacturer

DSP56364UM

24-Bit Audio Digital Signal Processor

Motorola => Freescale 

Freescale Semiconductor, Inc.

Signal/Connection Descriptions

Enhanced Serial Audio Interface

Table 1-10 Enhanced Serial Audio Interface Signals (continued)

Signal

Name

Signal Type

State during

Reset

Signal Description

FST

PC4

SCKR

PC0

SCKT

PC3

Input or output

Input, output,

or

disconnected

Input or output

Input, output,

or

disconnected

Input or output

Input, output,

or

disconnected

GPIO

disconnected

GPIO

disconnected

GPIO

disconnected

GPIO

disconnected

GPIO

disconnected

GPIO

disconnected

Frame Sync for Transmitter—This is the transmitter frame sync

input/output signal. For synchronous mode, this signal is the frame

sync for both transmitters and receivers. For asynchronous mode,

FST is the frame sync for the transmitters only. The direction is

determined by the transmitter frame sync direction (TFSD) bit in the

ESAI transmit clock control register (TCCR).

Port C 4—When the ESAI is configured as GPIO, this signal is indi-

vidually programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

Receiver Serial Clock—SCKR provides the receiver serial bit clock

for the ESAI. The SCKR operates as a clock input or output used by

all the enabled receivers in the asynchronous mode (SYN=0), or as

serial flag 0 pin in the synchronous mode (SYN=1).

When this pin is configured as serial flag pin, its direction is determined

by the RCKD bit in the RCCR register. When configured as the output

flag OF0, this pin will reflect the value of the OF0 bit in the SAICR regis-

ter, and the data in the OF0 bit will show up at the pin synchronized to

the frame sync in normal mode or the slot in network mode. When con-

figured as the input flag IF0, the data value at the pin will be stored in

the IF0 bit in the SAISR register, synchronized by the frame sync in nor-

mal mode or the slot in network mode.

Port C 0—When the ESAI is configured as GPIO, this signal is indi-

vidually programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

Transmitter Serial Clock—This signal provides the serial bit rate

clock for the ESAI. SCKT is a clock input or output used by all

enabled transmitters and receivers in synchronous mode, or by all

enabled transmitters in asynchronous mode.

Port C 3—When the ESAI is configured as GPIO, this signal is indi-

vidually programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

1-12

DSP56364 Advance Information

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

Share Link: