Specifications
Freescale Semiconductor, Inc.
Reset, Stop, Mode Select, and Interrupt Timing
2.9 RESET, STOP, MODE SELECT, AND INTERRUPT TIMING
Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing6
No.
Characteristics
8 Delay from RESET assertion to all pins at reset
value3
9 Required RESET duration4
• Power on, external clock generator, PLL
disabled
• Power on, external clock generator, PLL
enabled
• Power on, internal oscillator
• During STOP, XTAL disabled
(PCTL Bit 16 = 0)
• During STOP, XTAL enabled
(PCTL Bit 16 = 1)
• During normal operation
10 Delay from asynchronous RESET deassertion
to first external address output (internal reset
deassertion)5
• Minimum
• Maximum
13 Mode select setup time
14 Mode select hold time
15 Minimum edge-triggered interrupt request
assertion width
16 Minimum edge-triggered interrupt request deas-
sertion width
17 Delay from IRQA, IRQB, IRQD, NMI asser-
tion to external memory access address out
valid
• Caused by first interrupt instruction fetch
• Caused by first interrupt instruction
execution
Expression
—
50 × ETC
1000 × ETC
75000 × ETC
75000 × ETC
2.5 × TC
2.5 × TC
3.25 × TC + 2.0
20.25 TC + 7.50
4.25 × TC + 2.0
7.25 × TC + 2.0
Min Max Unit
— 26.0 ns
500.0 —
ns
10.0 —
ns
0.75 —
µs
0.75 —
ms
25.0 —
ms
25.0 —
ns
34.5 —
ns
— 211.5 ns
30.0 —
ns
0.0
—
ns
6.6
—
ns
6.6
—
ns
44.5 —
ns
74.5 —
ns
2-8
DSP56364 Advance Information
MOTOROLA
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