DSP56364P View Datasheet(PDF) - Motorola => Freescale
Part Name
Description
Manufacturer
DSP56364P Datasheet PDF : 162 Pages
| |||
Freescale Semiconductor, Inc.
Specifications
Reset, Stop, Mode Select, and Interrupt Timing
Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing6 (continued)
No.
Characteristics
Expression
Min Max Unit
18 Delay from IRQA, IRQB, IRQD, NMI asser-
tion to general-purpose transfer output valid
caused by first interrupt instruction execution
10 × TC + 5.0
105.0 —
ns
19 Delay from address output valid caused by first 3.75 × TC + WS × TC – 10.94 —
—
ns
interrupt instruction execute to interrupt request
deassertion for level sensitive fast interrupts1
20 Delay from RD assertion to interrupt request
deassertion for level sensitive fast interrupts1
3.25 × TC + WS × TC – 10.94 —
—
ns
21 Delay from WR assertion to interrupt request
deassertion for level sensitive fast interrupts1
• DRAM for all WS
(WS + 3.5) × TC – 10.94
ns
—
—
• SRAM WS = 1
(WS + 3.5) × TC – 10.94
—
—
• SRAM WS = 2, 3
(WS + 3) × TC – 10.94
—
—
• SRAM WS ≥ 4
(WS + 2.5) × TC – 10.94
—
—
24 Duration for IRQA assertion to recover from
Stop state
5.9
—
25 Delay from IRQA assertion to fetch of first
instruction (when exiting Stop)2, 3
• PLL is not active during Stop (PCTL Bit PLC × ETC × PDF + (128 K − 1.3 13.6 ms
17 = 0) and Stop delay is enabled
(OMR Bit 6 = 0)
PLC/2) × TC
• PLL is not active during Stop (PCTL Bit
17 = 0) and Stop delay is not enabled
(OMR Bit 6 = 1)
PLC × ETC × PDF + (23.75 ± 232.5 12.3
0.5) × TC
ns
ms
• PLL is active during Stop (PCTL Bit 17 =
1) (Implies No Stop Delay)
(8.25 ± 0.5) × TC
77.5 87.5 ns
MOTOROLA
DSP56364 Advance Information
2-9
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