DSP56366 View Datasheet(PDF) - Motorola => Freescale

Part Name

Description

Manufacturer

DSP56366

Digital Signal Processor

Motorola => Freescale 

Freescale Semiconductor, Inc.

Chip Errata

DSP56366 Digital Signal Processor

Mask:2J26D

Errata

Number

ES84

Errata Description

Description (added 5/13/98):

Applies

to Mask

2J26D

When software disables a DMA channel (by clearing the DE bit of the DCR)

, the DTD status bit of the channel may not be set if any of the following

events occur:

a. Software disables the DMA channel just before a conditional transfer

stall (Described by App B-3.5.1,UM).

b. Software disables the DMA channel at the end of the block transfer (that

is after the counter is loaded with its initial value and transfer of the last

word of the block is completed).

As a result, the Transfer Done interrupt might not be generated.

Workaround:

Avoid using the instruction sequence causing the conditional transfer stall

(See DSP56300 UM, App B-3.5.1 for description) in fast interrupt service

routines. Every time the DMA channel needs to be disabled by software, the

following sequence must be used :

bclr #DIE,x:M_DCR ; not needed if DIE is cleared

bclr #DE,x:M_DCR

; instead of two instructions above, one ’movep’ instruction may be

used

; to clear DIE and DE bits

movep #DCR_Dummy_Value,x:M_DCR

bclr #DE,x:M_DCR

nop

nop

Here, the DCR_Dummy_value is any value of the DCR register that complies

with the following requirements:

• DE is set;

• DIE is set if Transfer Done interrupt request should be generated

and cleared otherwise;

• DRS[4:0] bits must encode a reserved DMA request source (see the

following list of reserved DRS values);

List of reserved DRS[4:0] values (per device):

• DSP56302, DSP56309, DSP56303, DSP56304, DSP56362 — 10101-

11111

• DSP56305 — 11011

• DSP56301 — 10011-11011

• DSP56307 — 10111-11111

DSP56366 Errata

 1997 -2001, Motorola

For Mor3e66ICnfEo2rJm26aDt_io0n_0On This Product,

Go to: www.freescale.com

NG 11/12/01 pg. 4 of 25

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