DSP56366 View Datasheet(PDF) - Motorola => Freescale

Part Name

Description

Manufacturer

DSP56366

Digital Signal Processor

Motorola => Freescale 

Freescale Semiconductor, Inc.

Chip Errata

DSP56366 Digital Signal Processor

Mask:2J26D

Errata

Number

ES90

Errata Description

Description (added 6/25/98)/Modified 4/19/99:

Applies

to Mask

2J26D

A deadlock occurs during DMA transfers if all the following conditions exist:

1. DMA transfers data between internal memory and external memory through port

A.

2. DMA and the core access the same internal 0.25K memory module.

3. One of the following occurs:

a. The bus arbitration system is active, i.e., BG is changing, not tied to ground.

b. Packing mode (bit 7 in the AAR[3 - 0] registers) is active for DMA transfers on

Port A.

Workaround:

One of the following, but workarounds 2, and 3 are valid ONLY to section 3 a of the

errata - i.e. not valid if packing mode is used, and workaround 4 is valid only to

section 3 b of the errata - i.e., not valid if bus arbitration is active.

1. Use intermediate internal memory on which there is no contention with the core.

2. Tie BG to ground, or have an external arbiter that asserts BG even if BR is not

asserted.

3. Set the BCR[BRH] bit, whenever BR must be active.

4. Avoid using packing mode.

DSP56366 Errata

 1997 -2001, Motorola

For Mor3e66ICnfEo2rJm26aDt_io0n_0On This Product,

Go to: www.freescale.com

NG 11/12/01 pg. 5 of 25

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